basicaly each port is mainly made of its BSP :
https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp
And its SoC RTL :
https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/scala/saxon/board/radiona/ulx3s/Ulx3sSmp.scala#L34
I have to say, it is quite exotic ^^