Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
    emard
    @emard
    @edbordin ecppll has bugs in the float-to-integer math that calculates its internal parameters. I tried to make it better, integer-only and inside of the language, not the external script, so my hopfully better ecp5pll is here: https://github.com/emard/ulx3s-misc/tree/master/examples/ecp5pll
    Ed Bordin
    @edbordin
    @emard oh that's cool you can do it all in vhdl! maybe I will try to look at how your implementation works and see if I can help contribute bugfixes to ecp5pll for verilog users
    I actually found that when I tried to use the ecppll --highres output it caused nextpnr errors because it had connected CLKOP and CLKOS to the same net
    emard
    @emard
    Yes I managed to make the same both in vhdl and systemverilog. I havent implemented all the possible features, upgrades/pullrequests are welcome.
    Ed Bordin
    @edbordin
    I do like having the option to edit generated files, but your approach looks really easy to use! nice work :)
    e2kgh
    @e2kgh
    @ThomasHornschuh : I also work on a Win10 laptop and VMware. No problems writing my sdcard via USB.
    Niko-La
    @Niko-La
    Hi everyone. happy to join this lobby and learn about open source fpga :)
    Goran Mahovlic
    @goran-mahovlic
    @Niko-La Hi, and welcome!
    Lawrie Griffiths
    @lawrie
    My Pmod collection has now arrived from Crowdsupply.
    emard
    @emard
    pmods originals wow plenty of devices to add :)
    Dolu1990
    @Dolu1990
    @pnru_gitlab Emard got the good call, it was the holdn/wpn pins which where glitching because of crosstalk and possibily too week pullup XD
    Now it is solved
    all works
    and pushed in the dev-0.1 branch
    emard
    @emard
    Amazing news, I assembled remote RPI3 with ULX3S connected with USB to US1 port and with USB-FT2232 JTAG to GN pins for softcore CPU. RPI3 can remotely power cycle the board. Also LA was used with SOIC-8 clip directly to FLASH chip. And we found crosstalk at WP and HOLD lines that were confusing ISSI flash which didn't respond to 0xAB in this case
    @Dolu1990 had remotely logged to RPI3 and fixed saxonsoc to work :)
    Goran Mahovlic
    @goran-mahovlic
    wow!
    Paul Ruiz
    @pnru_gitlab
    @Dolu1990 @emard Congratulations!! What an excellent display of team work!
    What was the solution? Send the 0xAB command twice? Drive the HOLD and WP pins from the FPGA instead of relying on pull-up? Something else?
    Dolu1990
    @Dolu1990
    Just drive HOLD and WP to '1' strongly from the FPGA
    instead of relying on pull-up, right
    that was the only change required
    Paul Ruiz
    @pnru_gitlab
    So only the ISSI flash chips were problematic, right? So all the boards manufactured after March 2019 were fine even before this fix?
    Paul Ruiz
    @pnru_gitlab
    @lawrie You mentioned yesterday (or Saturday) that currently the --idcode option was no longer necessary when using a 12F with a 25F bitstream. Did I understand that correctly?
    Lawrie Griffiths
    @lawrie
    Yes, nextpnr now supports --12k and ecppack no longer requires the idcode.
    Paul Ruiz
    @pnru_gitlab
    If I use --12k, do I get the 12k capacity or the 25k capacity?
    Lawrie Griffiths
    @lawrie
    The 25k capacity.
    I believe that is all correct, but of course, @daveshah1 is the expert.
    Paul Ruiz
    @pnru_gitlab

    This stuff is moving so fast that it is hard to keep up with all the refinements :^)

    But that also means that for new ULX3S users it can be confusing. Even examples, projects and discussion threads from just 6 months ago can already be out of date. Kinda like Linux around 1997.

    Lawrie Griffiths
    @lawrie
    @emard The version of SaxonSoc with the flash fix is now in Smp/bitstreams/ulx3s_85f_green_2core_saxonsoc.bit
    emard
    @emard
    @lawrie wooow let me try this out of the box :). Now all known boards should boot saxonsoc, and the fix is now more future-proof becausw we know how to crrectly drive FLASH so its more future proof
    Lawrie Griffiths
    @lawrie
    I have not updated the other ones as we did not get problems on 12F or blue 85F, but they will get the fix next time I build them.
    Just noticed my push was rejected, but it is there now.
    emard
    @emard
    @pnru_gitlab yes too much issues so I put on hold cleaning up my ulx3s-examples, outdated. (I'm now even thinking about delete) :)
    Basically this example should demonstrate getting tools and compiling blink, nothing else no WSL, no ESP32 etc
    emard
    @emard
    @lawrie @Dolu1990 I downloaded 85F "green" 2-core bitstream from Smp flashed and it boots! RMII ETH works also! The iperf3 reports about 8 Mbps, the same as on 1-core 12F.
    Dolu1990
    @Dolu1990
    hmmm
    emard
    @emard
    It's probably propery of my eth switch or PC that tests it
    I found a bug in mcpclock, setting it to 1970-01-01 makes garbled year "d0" instead of "70"
    Dolu1990
    @Dolu1990
    I will have to investigate MAC / Sdcard performances, to see where linux is losing time
    Cool anyway ^^
    emard
    @emard
    Yes when it works out_of_the_box it is very comfortable to boot and login
    emard
    @emard
    mcpclock.c epoch years bug fixed and pushed - if in distribution, I recommend update :)
    @pnru_gitlab small bugfix, probaby your hwclock still has it :)
    -  v = tvp->tm_year; v -= 100; v = (((v/10)<<4) + (v%10));
    +  v = tvp->tm_year; v %= 100; v = (((v/10)<<4) + (v%10));
    e2kgh
    @e2kgh
    @lawrie : what is the magics of making the DTB files automatically? So far I get all my stuff to compile here for my green 85F, but the dtb, I stil have to copy from your GIT ...
    emard
    @emard
    @lawrie closing " in README :)
    date -s "2020-10-03 11:23
    Paul Ruiz
    @pnru_gitlab
    @emard thanks for the heads-up. For the Cortex RTC clock there are a bunch of updates that I need to do. By the way, has anybody ever tested the i2c link to the GDPI connector / monitor?
    My focus for the Cortex right now is mostly to make networking comfortable. Some of this stuff will also be needed for connecting it to a Blit.
    Lawrie Griffiths
    @lawrie
    @e2kgh Currently the dts for 2 and 4-core systems have to be edited by hand. You need to move the start of the commented-out code down here and here, and then run saxon_buildroot_dts.
    If you have 64MB od SDRAM, you have to change this line.