Well, fixing all clock cycles other than I/O or PROM being memory cycles improved things. With the new disk image I now get:
SD CMD = 510008004cff i = 90 SD CMD = 7a00000000ff SD CMD = 510008004dff i = 91 leds=00000084 leds=00000001 leds=00000002 leds=00000004 leds=00000020 memory bug!
in simulation. The leds= values are hex. So we get to "control transferred to the Kernel" before we go wrong. And we go wrong before there is a memory bug (i.e. cache output != shadow sram output).
reposting from discord: Has anyone found a good simulation model for the IS45S16160G sdram? (ideally verilog)
Very simplistic, but these worked for me:
The Cortex one does single word reads/writes with CL=3, the Oberonstation one does burst reads/writes with CL=3.
@emard @charlesap OK, thinking about the address bus stability with a fresh mind this morning lead to a minimal, 2 line fix to the RISC5 core and now it seems to work (in simulation) as it should. It continues to led=0x40, "Directory traversal complete" when te simulation time (200ms) ran out.
Will do a longer run, but it seems we are there on the simulation side.
How about a test without video at 125MHz? It would be good to know if that boots to the expected leds.
My simulation now ran for 400ms, but it is still doing stuff with the file system at that time.
ERROR: Failed to pack flipflop 'controller.dbi_FF._TECHMAP_REPLACE_' with 'syn_useioff' set into IOLOGIC. ERROR: Packing design failed.