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    Ed Bordin
    @edbordin
    reposting from discord: Has anyone found a good simulation model for the IS45S16160G sdram? (ideally verilog)
    Paul Ruiz
    @pnru_gitlab

    This last mem bug seems to be because the RISC5 CPU does not keep its address bus stable during a memory stall in all cases. I'm beginning to see why Fleaohm chose gating the clock as a brute force way out.

    .

    reposting from discord: Has anyone found a good simulation model for the IS45S16160G sdram? (ideally verilog)

    Very simplistic, but these worked for me:
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/ob_tb.v#L150-261
    https://gitlab.com/pnru/cortex/-/blob/master/sys_tb.v#L292-385

    The Cortex one does single word reads/writes with CL=3, the Oberonstation one does burst reads/writes with CL=3.

    Ed Bordin
    @edbordin
    thanks! I also just found this which was the sdram chip used on a different production run (I will have to take care to select the equivalent 256M size for it though) https://github.com/lgeek/orpsoc/blob/master/bench/verilog/mt48lc16m16a2.v
    Paul Ruiz
    @pnru_gitlab
    thanks! I've looked for something like that for a while, but never found one.
    Ed Bordin
    @edbordin
    I might give it a go, so long as I edit the timing parameters it looks like it should be good. Although given I'm using someone else's working sdram controller maybe this is overdoing it
    emard
    @emard
    @pnru_gitlab in my port of oberon here is OSD HEX overlay example where it can in real-time display any 64-bit wire as HEX overlaid on oberon screen. I must go2sleep() now, if you want me to add it to your code I can do it, just it needs VGA signal out and it will video mix HEX to it. https://github.com/emard/oberon/blob/master/hdl/top/ulx3s_v20_top.v#L175
    emard
    @emard
    OSD stuff is updated, holding BTN1 shows HEX LED, sdram_a, sdram_d over oberon video. HEX is updated during vsync to avoid "breaking" of digits. There is not much traffic on the bus, moving mouse pointer will change it for example.
    Paul Ruiz
    @pnru_gitlab

    @emard @charlesap OK, thinking about the address bus stability with a fresh mind this morning lead to a minimal, 2 line fix to the RISC5 core and now it seems to work (in simulation) as it should. It continues to led=0x40, "Directory traversal complete" when te simulation time (200ms) ran out.

    Will do a longer run, but it seems we are there on the simulation side.

    emard
    @emard
    Great news! I have HEX decoder and DVI video OSD ready to be used if you will need help in hardware debugging that shows any bus state in HEX in real time. mini display is not required.
    Paul Ruiz
    @pnru_gitlab
    @emard I've uploaded a new tarball. I've not tried synthesis at all yet. Video code is there, but commented out in the top file. I've renamed the prom images prom.mem (original) and prom_sim (charles version) with an ifdef in the PROM.v file for automatic selection of the right one.
    emard
    @emard
    I pulled and compiling
    Paul Ruiz
    @pnru_gitlab
    Thanks. Hopefully I will be able to do some h/w tests of my own late this evening.
    emard
    @emard
    Video is also enabled at toplevel what I see in the source, no commented out?
    Quiickly looking, OSD HEX could be inserted in the video stream at toplevel
    Paul Ruiz
    @pnru_gitlab
    I think in line 343-372 in Ulx3s_Top.v I have commented it out?
    emard
    @emard
    No, there's just comment text commented and code active
    It can be left as is especially if it generates any picture
    Paul Ruiz
    @pnru_gitlab
    In oberon_251020.tgz ?
    There may be a timing synthesis issue with video included, but maybe it works.
    It is not good if you don't see the commented out lines, because there were changes to the toplevel as well since yesterday.
    emard
    @emard
    yes oberon 251020. I compiled but no boot, Only D7 lit. Generates 1024x768 60Hz black screen, correct sync
    Oh sorry my mistake, yes you are right, I extracted wrong file
    Paul Ruiz
    @pnru_gitlab
    emard
    @emard
    I am compiling this with corrected memsel and video enabled
    emard
    @emard
    I compiled now latest 251020 but still the same effect only D7 lit and black screen
    Paul Ruiz
    @pnru_gitlab
    Uhm, i think i forgot to change pll.v back to 125 (0 deg) mhz.
    emard
    @emard
    You can use my ecp5pll.sv that's easy any setting
    Paul Ruiz
    @pnru_gitlab
    Yes.
    emard
    @emard
    My ecp5pll calculator reports that it can't fit parameters for 125,65,325 MHz to the same PLL and requires 2 different instances.
    your has generated 130MHz instead of 125 MHz which can't work
    BUT on 85F now there are not enough BRAM to support OSD HEX display :)
    Paul Ruiz
    @pnru_gitlab
    In general it should be able to work, but in this case I'm pushing it really close on timing. The SDRAM has data ready at "half a clock" as seen from the controller clock and I delay that by ~2ns. This means registered data is available 6ns after the controller clock positive edge. The cache block RAM clocks that in on the next positive edge. At 125MHz the cycle is 8ns, so the block RAM gets 8 - 6 = 2ns setup time. At 130ns it is even less.

    How about a test without video at 125MHz? It would be good to know if that boots to the expected leds.

    My simulation now ran for 400ms, but it is still doing stuff with the file system at that time.

    emard
    @emard
    I will compile it somehow with 125MHz to see what LEDs do
    emard
    @emard
    I compiled 125MHz but same as before D7 and no boot
    Paul Ruiz
    @pnru_gitlab
    Bummer - that can only mean that the sdram is not working. However, with the 12F yesterday getting a lot further in the sequence, I must be close. Back to the drawing board. Maybe that SDRAM test bench model that @edbordin located will help in pinning down the issue.
    emard
    @emard
    In video declaration there is 1 word too much reg [31:0] mem[0:24575]; while you used 24576
    Paul Ruiz
    @pnru_gitlab

    Another strange thing is that the screen is black - I think I am pre-filling the video ram with some content.

    Yes, you are right: 24575.

    emard
    @emard
    OK last word doesn't make it fit with OSD ...
    Paul Ruiz
    @pnru_gitlab
    You could reduce the size of video ram by half, just for testing. If the upper part of the screen works, probably the bottom half will too :^)
    emard
    @emard
    I will compile it this way
    Can't fit even with 8K words :(
    hex needs only 1 BRAM block for the font
    but who knows how yosys infers this all
    ERROR: Failed to pack flipflop 'controller.dbi_FF[0]._TECHMAP_REPLACE_' with 'syn_useioff' set into IOLOGIC.
    ERROR: Packing design failed.
    Paul Ruiz
    @pnru_gitlab
    This is strange - I am using 2KB for the PROM, 16KB for the cache and 96KB for video (48KB if you cut it in half). That should be a very easy fit on the 85F.
    emard
    @emard
    I don't know, now I will compile only OSD mixer without hex decoder just to find what's up
    maybe divison by 6 it makes build BRAMs for lookup tables, that can be disabled
    emard
    @emard
    It could be other problem, OSD HEX decoder may refuse routing to sniff traffic at IFS blocks