How about a test without video at 125MHz? It would be good to know if that boots to the expected leds.
My simulation now ran for 400ms, but it is still doing stuff with the file system at that time.
ERROR: Failed to pack flipflop 'controller.dbi_FF._TECHMAP_REPLACE_' with 'syn_useioff' set into IOLOGIC. ERROR: Packing design failed.
@sthornington I've not built from scratch for a while, so no recent experience. However, some 12 months ago I was building from scratch on Catalina and it took some time to get right (at that time the issue was with the boost libraries). In general, it seems to me that the Trellis build for OSX can be troubled from time to time.
The daily builds over at https://github.com/open-tool-forge/fpga-toolchain may be your best source of clues: they will probably be the first to notice something going wrong in the build. Their build scripts may also provide an answer for your issue.
@emard Maybe indeed there is a total failure of sdram, although I would surprised that it would get as far as leds=0x84 in that case. I am running tests with the sdram model that @edbordin found and that has already identified some issues (like my refresh commands being spaced too closely together).
Maybe the HEX interface can track the commands that are sent to the sd card? This way we can check that the sequence prior to leds=0x84 runs as expected or not.
@edbordin Point taken. However, I also have an older ulx3s board with the micron chip. In general, I guess I'd like to write it such that a wide range of chips are covered.
Further tests bring up no other issues, and inspection of the sdram and cache ram contents after a short run show the expected results.
@emard The sdram controller can work alone, but it is designed to read/write 128 (16 bit) word bursts. Not so easy to interface to a host that expects single words. The cache can really only work together with the sdram controller, because it expects signals and data to arrive in precise order (like: "if this signal is asserted, data will be available 2 clocks later", etc.). It could be possible to connect the cache/sdram combo a simple system with a monitor program.
Maybe the least effort is to write a simple RISC5 assembler and put some short test programs in the rom and test that way. Heresy, as in the minds of the Oberoners there is no such thing as RISC5 assembler, it seems. The Oberon system has a UART that is easy to use: write to a register and a character gets send, etc.
I am probably not seeing the forrest for the trees. I think I will leave this for a week and then have a fresh look.