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    Goran Mahovlic
    @goran-mahovlic
    We have added few USB/OV7670 extensions to e-radionica https://e-radionica.com/en/catalogsearch/result/?q=ulx3s
    still no pictures, but will be there
    Torfinn Ingolfsen
    @tingox_gitlab

    this might show my lack of verilog knowledge, but still. In the example https://github.com/lawrie/ulx3s_cpm_z80 in the file Microcomputer.v I find this little snippet:

       // ===============================================================
       // System Clock generation
       // ===============================================================
       wire clk125, clk;
    
       pll pll_i (
         .clkin(clk25_mhz),
         .clkout0(clk125),
         .clkout1(clk)
       );

    But no further definition in any file related to this project. Is this some kind of built in primitive for verilog? (I couldn't find a description in Lattice ecp5 documents, so I don't think it comes from there). How is one supposed to figure out what 'clk125' and 'clk' are? (ok, I might guess that clk125 is 125 MHz, but that is just a guess).

    Lawrie Griffiths
    @lawrie
    Torfinn Ingolfsen
    @tingox_gitlab
    never mind, I just found the pll.v file that comes with the project blush
    Paul Ruiz
    @pnru_gitlab
    I wrote a simple assembler for the Oberon RISC5 cpu and with that some simple test programs for the Oberon rom:
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/as5.c
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/test.s
    To my surprise, the cache does not seem to read from sdram at all, and just keeps showing the pre-loaded content. A small anomaly every 64 words suggests that it does recognize cache lines and updates the tag for the line. This overall outcome surprised me: I had expected it so see it read garbage or maybe data with a location offset, etc.
    Then I configured a simple 99K system with the cache + sdram (and a bit of rom and bram for a monitor). With that system the cache + sdram mostly works, there is some data corruption that suggests my timing is not quite right but otherwise results are as expected.
    Krome Plasma
    @kromulan
    Where is ULX3s sold ? I mean where can i buy the board ECP5 85F?
    Ed Bordin
    @edbordin
    you can preorder from the next batch of 85F on crowdsupply or mouser. I'm not sure if Radiona sells through other channels too
    Goran Mahovlic
    @goran-mahovlic
    @kromulan I have 85F prepared for CrowdSupply, but currently waiting for some papers from them.
    And currently no other chanels for 85F
    emard
    @emard
    @pnru_gitlab hey cool small source of assembler!! Obviously risc5 cpu presents some bus transitions that confuse the cache. Generally it is possible that cache and ram controller have a bug which doesn't manifest when used on one soft-core because it has always the same access pattern, while on other core the bug may manifest
    Charles Perkins
    @charlesap
    @pnru_gitlab An excellent little assembler! I will now abandon my efforts to make one in Python because this one does everything I would need.
    emard
    @emard
    ULX3S v3.1.4 project is out https://github.com/emard/ulx3s maybe you alread know, but I just tried and it works, small vt100 onboard editor for esp32 https://github.com/emard/esp32ecp5#onboard-editor
    mara
    @vmedea
    that could definitely come in useful ! at least with the memory to spare
    Andrew Nesbit
    @ullbeking_gitlab
    :'-( :'-( :'-( Waaaahhhh!! I was SO EXCITED when this was being lobbied for and I was pledging for it. Then it was finally released and guess what, I am completely and utterly broke, and there's no way I can rationalize buying this now :'-( I thinkit will make it all the more sweet when I finally DO save up some money and finally am able to buy it myself. It will mean so much more to me then.
    emard
    @emard
    @ullbeking_gitlab production really took much time. If I click "mouser" at https://kitspace.org/boards/github.com/emard/ulx3s/ parts for 85F without PCB cost 93$. Design goal asked by FER uni was that 200-500 assembled boards cost approx equal as parts from one set from mouser For student buying at FER shop, less than 100$ per board. Price at CS is only exceeded by administrative amount, but it is still very tight, Goran must work really hard to get any income from this - if there is more than 8% of faulty boards from production it would mean loss of investition. Even I don't have latest v3.0.8 85F because Goran sent all to CS distribution. It is always unsure will new v3.1.4 or higher prototype, when assembled, work as expected.
    Goran Mahovlic
    @goran-mahovlic
    I am trying to organize production with e-radionica for 12F without some chips - like ADC/I2C/RTC that version would be in the e-radionica store so we would not pay for extra shipping/export/import/fees so it should be more affordable.
    One 100 pcs. production run is requested from Watterot - but we are waiting really long time for them. I also do not think it will be cheaper, it will only have 64Mb SDRAM - as the first batch they did...
    Goran Mahovlic
    @goran-mahovlic
    As for Crowd Supply - in after sale I really lowered all prices for them - as in campaign (after lots of negotiations) they offered good fee - almost too good, so they did not have any profit on campaign boards. Specially after sending all those "free" connectors in separate shipment.
    Michael Engel
    @michaelengel
    Yeah, the separate connectors (which came in a rather large package) were a bit of a surprise...
    Paul Ruiz
    @pnru_gitlab

    I've now got the cache to work reliably for the 99K system:
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/cache.v
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/sdram.v

    NextPNR reports an Fmax of ~65MHz, but this seems wrong: I've tested with the cache/sdram running at 90MHz and 130MHz (CPU clocked at 25MHz) and both work just fine. I've not drilled down to the bottom of this, but probably NextPNR sees a limit on a signal that is stable for more than one clock.

    I was stuck for a long time on something that appears to be a Yosys/NextPNR bug. If I'm not mistaken, this does not work:

    reg   [0:SETS-1] dirty[0:WAYS-1];
    dirty[way][set] <= dirty[way][set] | wr;

    (appears to always set bit 15 regardless of the value of 'set') and this does work as expected:

    reg   [SETS-1:0] dirty[0:WAYS-1];
    dirty[way][set] <= dirty[way][set] | wr;

    (note reversal of bit range).

    Paul Ruiz
    @pnru_gitlab
    I hope to get back to the Oberonstation next week.
    David Shah
    @daveshah1
    @pnru_gitlab the indexing issue sounds like a Yosys issue to me
    as for the timing, that is because the FPGAs are turning out to be a lot better than Lattice specify these days
    -6 and -8 speed grades are essentially indistinguishable in practice
    Paul Ruiz
    @pnru_gitlab

    @daveshah1 The problematic line appears to be:
    https://gitlab.com/pnru/ulx3s-misc/-/blob/master/oberonstation/cache.v#L144
    If I change that to a posedge the calculated Fmax goes up to ~130MHz. Originally that line was just an assign, but that left occasional data corruption. If I just register sdr_ctr[0] on negedge, Fmax is also calculated to about 130MHz.

    Maybe the circuit is helped by the block ram being sequentially accessed and staying in a single row; this may lead to an access time well less than 10ns ??

    emard
    @emard
    I made ESP32 micropython DCF77 fake sender which doesn't work :) https://github.com/emard/DCF77/tree/master/micropython I tried best I can and signal on the scope looks as it should be. But clocks don't recognize the carrier. I don't know do I have wrong clocks or too noisy environment so it can't work. If anyone sees anything wrong in my code let me know
    Thomas Hornschuh
    @ThomasHornschuh
    HI, I have a question about MASTER_SPI_PORT=ENABLE or DISABLE. Diamond tells me that I can only access flash pins from Bitstream with set to DISABLE. This is also stated on the comment in the standard .lpf file. With ENABLE it states "write to FLASH possible any time from JTAG:" . Does it mean, that after Bitstream load with set to DISABLE further FTP put over ESP32 will fail?
    mara
    @vmedea
    in general no, no matter what the bitstream does (as long as it keeps wifi_en=1 so that the ESP32 remains on) it doesn't prevent the ESP32 from flashing or programming
    Simon Thornington
    @sthornington
    is there an example of handling a button press on the esp32 in micropython, given the passthru bitstream? I am having trouble searching for this
    emard
    @emard
    @ThomasHornschuh It actually means that while bitstream is running, it is possible to write flash without interrupting of the bitstream for special applications which need minimal downtime. currently esp32ecp5 will always unload bitstream but you can disable this in the source.
    In most of our retrocomputing examples (take any from @lawrie QL, spectrum, vic20) or @Speccery it uses spi slave in FPGA and gpio0 interrupt pin. using current passthru bitstream is for C but not recommended from micropython as passthru communicates with SD card lines, expecting to unmount and release all SD lines, which is not possible with micropython but possible with C
    emard
    @emard
    DCF77 update: it started to work. Wiki documentation is wrong about modulation level. Modulated amplitude must go down to 25% of full level (100% value).
    Simon Thornington
    @sthornington
    Okay thanks I was just curious. I don’t really plan to do a whole whack of stuff in micropython, it was just handy to test the nonstandard OLED display I stupidly bought
    emard
    @emard
    I have examples for SSD1331, SSD1351, SSD1306 OLED displays
    Simon Thornington
    @sthornington
    Yeah i worked from your ssd1331 and the spec to get my ssd1327 working. Going to do st7789v next
    Simon Thornington
    @sthornington
    I have a question - are the oled and lcd examples, with the custom bitstream for the latter, rearranging the pins to conform to the lcd display or something (and therefore no longer match what's printed on the PCB?)
    because I've been making custom cables to match the PCB markings but now I'm getting confused between oled.py where self.gpio_csn = Const(17) but in top_st7789.v lcd_clk = wifi_gpio17;
    (and I am kinda assuming the 17 here refers to the same thing)
    Simon Thornington
    @sthornington
    perhaps this has to do with the oled example using SPI channel 1 but the LCD example using SPI channel 2
    maybe I literally need to read three years of scrollback in this gitter to get the gist
    emard
    @emard
    @sthornington yes bitstream projects do rearrange pins. At least GND and 3.3V must match, FPGA is flexible about pins, practical is to plug display directly without wires. Original markings are for SSD1331. ST7789 7-pin is similar but I think pin has BL (backlight) function instead of CS. wifi_gpio17 refers to the same thing and also ESP32 is flexible about SPI pinout so you can match practicaly any combination.
    esp32 Channels 1 or 2 itself are the same but if you mount SD card from ESP32 it will always use channel 1 so channel 2 remains free. Without SD channel 1 or 2 are for display the same.
    emard
    @emard
    For easy BTNs you can use simple FPGA logic to connect e.g. BTN0 to wifi_gpio0 and some other similar, directly in FPGA logic, simple approach
    Simon Thornington
    @sthornington
    @emard understood, I guess one way to make it so you could always plug in would be to put another gnd/vcc in the opposite order on the other side :). I think I need to read the schematic & pcb and try to match it up with the constraints or something, the OLED pins are not marked with their "site", only the ssd1331 defaults so it's a bit confusing.
    Simon Thornington
    @sthornington
    @emard (to be clear, the way I read the above is that the gnd and 3.3v are the two pins that cannot be rearranged by the fpga) ?
    emard
    @emard
    @sthornington of course GND and VCC can't be swapped by FPGA, because OLED draws current and must connect to hard power supply, can't be powered from FPGA 16mA pins (so low power devices actually could swap even GND/VCC). new board will have 8-pin LCD header instead of 7-pin but there's really crowded with routing so additional 2 pins are nearly impossible. But if display has GND and VCC swapped, then it will fit to external connector GN/GN 0-27 so there's still a possibility to plug such display directly on board on the side
    Simon Thornington
    @sthornington
    @emard understood.