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    emard
    @emard
    For easy BTNs you can use simple FPGA logic to connect e.g. BTN0 to wifi_gpio0 and some other similar, directly in FPGA logic, simple approach
    Simon Thornington
    @sthornington
    @emard understood, I guess one way to make it so you could always plug in would be to put another gnd/vcc in the opposite order on the other side :). I think I need to read the schematic & pcb and try to match it up with the constraints or something, the OLED pins are not marked with their "site", only the ssd1331 defaults so it's a bit confusing.
    Simon Thornington
    @sthornington
    @emard (to be clear, the way I read the above is that the gnd and 3.3v are the two pins that cannot be rearranged by the fpga) ?
    emard
    @emard
    @sthornington of course GND and VCC can't be swapped by FPGA, because OLED draws current and must connect to hard power supply, can't be powered from FPGA 16mA pins (so low power devices actually could swap even GND/VCC). new board will have 8-pin LCD header instead of 7-pin but there's really crowded with routing so additional 2 pins are nearly impossible. But if display has GND and VCC swapped, then it will fit to external connector GN/GN 0-27 so there's still a possibility to plug such display directly on board on the side
    Simon Thornington
    @sthornington
    @emard understood.
    Simon Thornington
    @sthornington
    This message was deleted
    Paul Ruiz
    @pnru_gitlab

    @daveshah1 I'm trying to understand the speed of certain circuits. In a write-back cache I have to maintain a 'dirty bit' for each cache line.

    If I implement that as:

    reg   [SETS-1:0] dirty[0:WAYS-1];
    dirty[way][set] <= dirty[way][set] | wr;

    I seem to get to about 14ns delay, Fmax ~70MHz.

    Using a one-dimensional, wide vector seems a bit better

    reg   [WAYS*SETS-1:0] dirty;
    dirty[{way, set}] <= dirty[{way, set}] | wr;

    and reports about 10ns, Fmax ~100MHz.

    Using 4 different 16-bit vectors is better again (1 of 4 shown):

    reg   [SETS-1:0] dirty0;
    if (way==0) dirty0[set] <= dirty0[set] | wr;

    and reports about 8ns, Fmax ~125MHz.

    These are all NextPNR reports for an 85F as part of a larger circuit, not an isolated example. Are the above outcomes in line with your expectations and is there an even faster way to express the same?

    Ed Bordin
    @edbordin
    @emard I found in the chat logs here that you also hit this error with yosys -abc9: ERROR: Assert '!aig_map.count(bit)' failed in backends/aiger/xaiger.cc:435. Did you ever find out what the cause was?
    emard
    @emard
    @edbordin I don't know details, one of workarounds is to try to use or not to use -abc9 and/or --router router2. I don't remember exactly but this error could appear also while compiling some more complex design like oberon when some full featured BRAM couldn't be inferred and the workaround was actually to not infer but use vendor-specific BRAMs.
    Thomas Hornschuh
    @ThomasHornschuh
    Hi, I try to access the RTC from FPGA. Is there any special thing to take into account, because I have no success. Most likely some error in my design, but before digging into it I just want to know if there are pitfalls I'm not aware of
    emard
    @emard
    @ThomasHornschuh there are multiple possibilities. There are self-test binaries that show clock ticks. Saxonsoc linux has full support https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/Smp for RTC, get my https://github.com/emard/hwclock4saxonsoc and it will natively compile with saxon lcc. There are some ESP32-RTC related demos here https://github.com/emard/ulx3s-misc/tree/master/examples/rtc https://github.com/emard/ulx3s-misc/tree/master/examples/lcd_st7789/micropython/st7789_240x240_polyline/esp32
    Usually you need CR1225 3V lithium battery + polarity to metalic holder, - polarity to PCB pad. RTC can run without battery but for shutdown battery is mandatory.
    Thomas Hornschuh
    @ThomasHornschuh
    My question was meant in a different direction: I want to know if the RTC should work when the I2C io port of my RTL design is just mapped to pins in the reference I/O constraint file, or if the can be interference with e.g. esp32.
    emard
    @emard
    There is example https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/i2c_master/proj which makes i2c master in verilog, talks to RTC and displays time as HEX on DVI and LCD. There can't be interference with ESP32 because ESP32 is not directly connected to RTC, FPGA is between them.
    emard
    @emard
    @pnru_gitlab I can only speculate, but last notation looks like dirty0 is allowed to be placed to location independent of dirty1 etc (other examples make array and possible tie them all together) and this scatterness maybe results in a big design more optimally placed and routed = faster circuirt.
    cybermancer
    @cybermancer_gitlab
    Just ordered a ULX3S with ECP5 85F from Crowdsupply. However I am now confused as I hear there is supposedly a 32MB and a 64MB version of this board available... Obviously I would prefer a 64MB version if they exist but don't recall there bing any such option. What gives?
    Goran Mahovlic
    @goran-mahovlic
    @cybermancer_gitlab 64Mb version was just one run by Watterot, and they are not available
    On CrowdSupply only 32Mb is/was available.
    Good news is that boards are on the way to CrowdSupply - I managed to get all papers to send them last week.
    Currently by the tracking they are in Germany...
    Paul Ruiz
    @pnru_gitlab

    @emard Thanks for pointing that out, I had not considered the routing aspect yet. So far I figured that only the last form would be recognized as synthesizable to a physical DPR16X4C block (i.e. using the LUT config bits as distributed ram) -- but my understanding of Yosys/NextPNR is too limited to be sure about this.

    I don't have a lot of time right now, but I'm working through variations to make the cache design as timing independent as possible, so that it 'just works' for various bus designs. In the case of Oberon this is a little complicated as the RISC5 CPU has several (bus-)multiplexers after its registered signals, meaning that it takes until well into the clock cycle before its bus signals are stable. It does not help that the "memory not ready" input is indirectly also driving the address multiplexer leading to a logic loop in a straightforward asynchronous cache hit circuit.

    The current, working Next186-based Oberon design solves this by gating the Oberonstation system clock, which has its own issues as we discovered a few weeks ago.

    Paul Ruiz
    @pnru_gitlab
    @emard is it possible on the ECP5 to generate a PLL clock-out with e.g. 75% duty cycle? Or are the only routes (i) to start with a higher frequency; or (ii) using a 2nd phased clock?
    emard
    @emard
    @pnru_gitlab As far as I know duty cycle is always 50%. If you need to time something in the middle, the best way is to generate another clock phase shifted. If you use 125 MHz this clock is high enough, having 250 or 375 MHz may introduce even more routing problems so I'd say then it's better to generate second 125 MHz clock phase shifted instead of using higher rates.
    promach
    @promach
    @goran-mahovlic will a new version of PCB of ulx3s be released soon since the github files are modified recently ?
    Goran Mahovlic
    @goran-mahovlic
    @promach we will have only few pcs. probably 3 until - I do not think it will be available soon on mouser or CS
    emard
    @emard
    The github is direct where design and development is. There are new features, requires writing new code for testing. Some who want to risk (like us:) have already ordered parts and will assemble few boards and will let you know if it works. Complete design with parts ordering info is online, so it is also possible to request independent assembly of the boards, it should be not so much expensive, I expect maybe 150-200$ per board for order of 10 assembled boards
    Goran Mahovlic
    @goran-mahovlic
    and yes we will let you know if ordering advanced PCB from JLCPCB works
    currently on other project that has most ULX3S parts I can talk with ECP5
    I think empty boards price for 10 ULX3S on JLCPCB is around 60€
    Krome Plasma
    @kromulan
    It's like 5eur difference between 5 pcs and 10
    Goran Mahovlic
    @goran-mahovlic
    yes
    usually you can get 100 pcs. for 200€
    Krome Plasma
    @kromulan
    It's funny how little prices differ at higher quantities.
    Goran Mahovlic
    @goran-mahovlic
    yes, as most time is lost on preparing for design
    Krome Plasma
    @kromulan
    :)
    Goran Mahovlic
    @goran-mahovlic
    it is unlucky that ULX3S does not offer reorder for same design
    Krome Plasma
    @kromulan
    What do you mean ?
    Goran Mahovlic
    @goran-mahovlic
    it is offered by some manufacturers - so if design is successful you can just pay boards
    Krome Plasma
    @kromulan
    Ahh
    Bulk prices
    Goran Mahovlic
    @goran-mahovlic
    Well they already have my design
    so they will charge you 50€ for reusing same design
    as I ordered before you :)
    you could just buy boards for few $
    same will happen if I reorder boards
    Krome Plasma
    @kromulan
    Ohh :(
    Goran Mahovlic
    @goran-mahovlic
    I think I will pay all work again
    and get 10 pcs. for 60€
    Krome Plasma
    @kromulan
    You mean i would pay more since i used same design in my order actually ?
    That's without shipping btw ?