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    emard
    @emard
    @pnru_gitlab I can only speculate, but last notation looks like dirty0 is allowed to be placed to location independent of dirty1 etc (other examples make array and possible tie them all together) and this scatterness maybe results in a big design more optimally placed and routed = faster circuirt.
    cybermancer
    @cybermancer_gitlab
    Just ordered a ULX3S with ECP5 85F from Crowdsupply. However I am now confused as I hear there is supposedly a 32MB and a 64MB version of this board available... Obviously I would prefer a 64MB version if they exist but don't recall there bing any such option. What gives?
    Goran Mahovlic
    @goran-mahovlic
    @cybermancer_gitlab 64Mb version was just one run by Watterot, and they are not available
    On CrowdSupply only 32Mb is/was available.
    Good news is that boards are on the way to CrowdSupply - I managed to get all papers to send them last week.
    Currently by the tracking they are in Germany...
    Paul Ruiz
    @pnru_gitlab

    @emard Thanks for pointing that out, I had not considered the routing aspect yet. So far I figured that only the last form would be recognized as synthesizable to a physical DPR16X4C block (i.e. using the LUT config bits as distributed ram) -- but my understanding of Yosys/NextPNR is too limited to be sure about this.

    I don't have a lot of time right now, but I'm working through variations to make the cache design as timing independent as possible, so that it 'just works' for various bus designs. In the case of Oberon this is a little complicated as the RISC5 CPU has several (bus-)multiplexers after its registered signals, meaning that it takes until well into the clock cycle before its bus signals are stable. It does not help that the "memory not ready" input is indirectly also driving the address multiplexer leading to a logic loop in a straightforward asynchronous cache hit circuit.

    The current, working Next186-based Oberon design solves this by gating the Oberonstation system clock, which has its own issues as we discovered a few weeks ago.

    Paul Ruiz
    @pnru_gitlab
    @emard is it possible on the ECP5 to generate a PLL clock-out with e.g. 75% duty cycle? Or are the only routes (i) to start with a higher frequency; or (ii) using a 2nd phased clock?
    emard
    @emard
    @pnru_gitlab As far as I know duty cycle is always 50%. If you need to time something in the middle, the best way is to generate another clock phase shifted. If you use 125 MHz this clock is high enough, having 250 or 375 MHz may introduce even more routing problems so I'd say then it's better to generate second 125 MHz clock phase shifted instead of using higher rates.
    promach
    @promach
    @goran-mahovlic will a new version of PCB of ulx3s be released soon since the github files are modified recently ?
    Goran Mahovlic
    @goran-mahovlic
    @promach we will have only few pcs. probably 3 until - I do not think it will be available soon on mouser or CS
    emard
    @emard
    The github is direct where design and development is. There are new features, requires writing new code for testing. Some who want to risk (like us:) have already ordered parts and will assemble few boards and will let you know if it works. Complete design with parts ordering info is online, so it is also possible to request independent assembly of the boards, it should be not so much expensive, I expect maybe 150-200$ per board for order of 10 assembled boards
    Goran Mahovlic
    @goran-mahovlic
    and yes we will let you know if ordering advanced PCB from JLCPCB works
    currently on other project that has most ULX3S parts I can talk with ECP5
    I think empty boards price for 10 ULX3S on JLCPCB is around 60€
    Krome Plasma
    @kromulan
    It's like 5eur difference between 5 pcs and 10
    Goran Mahovlic
    @goran-mahovlic
    yes
    usually you can get 100 pcs. for 200€
    Krome Plasma
    @kromulan
    It's funny how little prices differ at higher quantities.
    Goran Mahovlic
    @goran-mahovlic
    yes, as most time is lost on preparing for design
    Krome Plasma
    @kromulan
    :)
    Goran Mahovlic
    @goran-mahovlic
    it is unlucky that ULX3S does not offer reorder for same design
    Krome Plasma
    @kromulan
    What do you mean ?
    Goran Mahovlic
    @goran-mahovlic
    it is offered by some manufacturers - so if design is successful you can just pay boards
    Krome Plasma
    @kromulan
    Ahh
    Bulk prices
    Goran Mahovlic
    @goran-mahovlic
    Well they already have my design
    so they will charge you 50€ for reusing same design
    as I ordered before you :)
    you could just buy boards for few $
    same will happen if I reorder boards
    Krome Plasma
    @kromulan
    Ohh :(
    Goran Mahovlic
    @goran-mahovlic
    I think I will pay all work again
    and get 10 pcs. for 60€
    Krome Plasma
    @kromulan
    You mean i would pay more since i used same design in my order actually ?
    That's without shipping btw ?
    Goran Mahovlic
    @goran-mahovlic
    well you will pay as I did not already payed for all preparation
    but they already have all needed to just print you 10 pcs. of board
    Krome Plasma
    @kromulan
    You mean they actually won't care that your design was already paid from you it's like always starting over again...
    Goran Mahovlic
    @goran-mahovlic
    I do not know how they work - but I assume they are smart :)
    Krome Plasma
    @kromulan
    But if they did support that then everyone would benefit basically right ?
    Goran Mahovlic
    @goran-mahovlic
    yup!
    Krome Plasma
    @kromulan
    Goran maybe you should ask them on chat
    Goran Mahovlic
    @goran-mahovlic
    except they would get less money :)
    Krome Plasma
    @kromulan
    Not necessary if people ordered
    They probably get more money on less quantity anyway
    That is from many different customers
    Goran Mahovlic
    @goran-mahovlic
    well they will as they always charge preparation
    Krome Plasma
    @kromulan
    Yes
    Goran Mahovlic
    @goran-mahovlic
    maybe