Info: Annotating ports with timing budgets for target frequency 12.00 MHz ERROR: cell type 'twowaycache' is unsupported (instantiated as 'myfampiga.mysdram.mytwc')
@tingox_gitlab : you have problems with ghld on tg68k, or minimig? I think/remember, that Till had a setup to simulate in ghdl, when he made Mist ...
Actually, I have too little experience with both ghdl and minimig code to be able to say which it is. Previous experience with minimig has been mostly adjusting existing projects (made by others) to a new board (with altera or xilinx fpga), but still using vendor tools (quartus / ise). Also, it is clear now that ghdl requires a different (higher) level of correctness for the vhdl code compared to vendor tools.
I'm not sure that will work; I tried loading the precompiled bitstream (from https://github.com/litex-hub/linux-on-litex-vexriscv-prebuilt) but then fujprog complained
tingo@kg-core2$ fujprog build/ulx3s/gateware/top.svf ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 12K v3.0.8 Found LFE5U-12F device, but the bitstream is for LFE5U-45F. Failed.
unless there is a way to override fujprog checking?
@Speccery Excellent stuff on the Icy99 project. I'm seriously impressed.
On the QL: If the original sound on your QL still works, it might be worth to compare its output with that of the FPGA version. What we have today is based on reverse engineering the 8049 code and creating an equivalent direct circuit -- we are not sure the output is (roughly) correct.
On the microdrives there is an outstanding work item: implementing writes to the disk. The current FPGA/ESP32 design allows for it, but it is currently unimplemented.