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    emard
    @emard
    @tingox_gitlab No but bitstream.svf contains same bitstream reverse hex printed
    there is bit2svf.py also in trellis so you need own svf2bit, should be rather simple to make
    Simon Thornington
    @sthornington
    not that anyone here is interesting I am sure, but I got the (LiteX) wishbone debug bridge over US2 working with the main/master branch of the valenty USB core (DummyUsb endpoint). Seems reliable with cdc support enabled. But, SoC reset causes both US2 debugging as well as US1 JTAG programming to fail until unplug/replug
    Simon Thornington
    @sthornington
    random question - for ulx3s ECP5 85F, what FMAX should I be "happy with" ? Trying to recalibrate coming from Xilinx, it seems like 100MHz is quite hard to achieve ?
    emard
    @emard
    For well designed pipelined small cpu/soc 100MHz (f32c) should be possible but on the edge. For SDRAM driver 125 MHz should also easily always possible (overclocked ram test go to 180-200MHz). Small parts like video DVI shifter can do 350 MHz (overclocked work up to 600MHz, no guarantee all boards). Big soc like linux about 50MHz for CPU core, RAM 100MHz.
    Simon Thornington
    @sthornington
    Thanks, that helps
    Simon Thornington
    @sthornington
    I'm placing a small design on a big FPGA, are there any guides to encouraging nextpnr to place things closer together? for instance, I get much higher fmax targeting a 12F than an 85F
    Lawrie Griffiths
    @lawrie
    @sthornington That is impressive getting the the wishbone debug bridge working with a gateware usb implementation. Did you ever have it working on us1? There seems to be renewed interest in the LiteX SoC amongst newer Ulx3s users. I must give it a go sometime. I have recently been learning nmigen, and I have been a bit reluctant to learn migen as well. The nmigen USB device implementation in the Luna project should be a replacement for ValentyUSB.
    Which Risc-V implementation are you using with LiteX? Is it VexRiscv?
    Paul Ruiz
    @pnru_gitlab
    @lawrie Thinking about that interrupt in your MacPlus. I assume that this Mac uses interrupt auto-vectoring?
    @sthornington not that anyone here is interested I am sure wrong: I figure folks around here are interested.
    Lawrie Griffiths
    @lawrie
    Yes, I am pretty sure it uses auto-vectoring.. I am just about to push my current code, which sets auto-vectoring in the same way as the QL.
    I am planning to put back the SPI ram code that I could out from the QL version, so I can try reading and writing the SDRAM from the ESP32, as I am still not sure if it working in the normal case.
    The SDRAM test seems to be working, but does not seem to be detecting as much SDRAM as it should.
    Paul Ruiz
    @pnru_gitlab
    It could be that the autovector cycle interferes with the first vector read. If only looking at AS, UDS and LDS, the autovector cycle looks like a memory read cycle.
    Lawrie Griffiths
    @lawrie
    I push my latest changes. This is where I set vpa_n - https://github.com/lawrie/ulx3s_mac128/blob/main/src/mac128.v#L194
    I am unsure whether to set vpa_n for peripheral addresses, as I don't think the Mac needs the 68000 peripheral bus. It does not seem to make much difference if I set it for peripheral addresses or not. If I do set it, then I need to use vma_n.
    The symptoms are consistent with the first vector read going wrong, but when I added code to the cpu_din multiplexer to force the read of address $64 to return $400000, it did not help.
    Lawrie Griffiths
    @lawrie
    The symptoms are that the interrupt routine seems to be running code that makes no sense.
    Paul Ruiz
    @pnru_gitlab
    One useful test could be to replace the first 1024 bytes of RAM with block ram and see if that makes a difference. That will confirm / rule out sdram as the issue. Note that there is a typo in your ram module:
    https://github.com/lawrie/ulx3s_mac128/blob/main/src/ram.v#L8
    to force the read of address $64 to return $400000
    I assume you meant $40, to create address $0040xxxx?
    Lawrie Griffiths
    @lawrie
    Yes
    Thanks for pointing out the bug in ram.v. That must be in the QL version as well, but I am not currently using it for either project.
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab i wrote the first 1024 words to BRAM as well as SDRAM so I can choose which one to set cpu_din to. It did not solve my problem with interrupts, so there must be another problem. However I still get the issue that I never see $40 read back from address $64 from SDRAM, but I do see it from BRAM.
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab I added the esp32 spi ram interface and the SDRAM interface seems to be working:
    >>> print(''.join('{:02x}'.format(x) for x in osd.peek(0x64,4)))                                                                                      
    00401a42
    emard
    @emard
    Could it be that 68k has some bus protocol during interrupts that on the data and addr bus appear some data related to interrupt priority and it's source, which may be fooling sdram driver which is for example only tested to work with stable bus state and clean requests when RAM data perisist on bus all the time during the RAM cyclue
    Lawrie Griffiths
    @lawrie
    That might be the case, but I am now using BRAM for low ram addresses, which ought to fix that. So my current problem is that the level 1 (VIA) interrupt does not work. It gets stuck in the rom at address $1942, but I am pretty sure if shouldn't be there. I tried patching the level 1 interrupt routine at $1A42 to do an immediate RTE, but that makes no difference, suggesting that it is jumping somewhere else for the interrupt.
    emard
    @emard
    Oh we had some VIA blues from VIC20 too, was hard to fix, mostly analyzing the code and writing fake VIA which matched to existing keyboard scan routine :)
    Paul Ruiz
    @pnru_gitlab

    I think we may have two different errors here. The first is that the sdram read appears to malfunction immediately after an autovector cycle. This I can verify in simulation. My hypothesis is that in between the autovector bus cycle and the read bus cycle an sdram refresh cycle is started, which causes the sdram read cycle to start late and hence data to arrive too late. This hypothesis can also be checked by slowing down the CPU.

    The second is that the interrupt vector seems to be interpreted wrong, regardless of whether it is hardcoded in verilog, coming from sdram or block ram. Is it possible that the interrupt signal is withdrawn too early, and the CPU is taking the "spurious interrupt" vector instead?

    Lawrie Griffiths
    @lawrie
    I agree that it seems to be two errors.
    Lawrie Griffiths
    @lawrie
    I don't think the interrupt is withdrawn too soon. It needs to execute code to write to VIA registers to withdraw the interrupt.
    It looks a bit like the SCC interrupt is executed rather than the VIA one, as the code it gets stuck in is related to the SCC (serial chip).
    But i can't currently see how that could happen.
    The Mac has just the two interrupts, VIA (level 1) and SCC (level 2).
    Simon Thornington
    @sthornington
    @lawrie I never tried doing the debug bridge over US1, I figured it was hardwired to the FTDI which was being used to program and as a serial console for the SoC. Should I have been ableFwiw the main reason I am using LiteX is because the svd file helps write HAL layers in Rust more easily, I’m not particularly taken with nmigen.
    Hmm editing not working, wanted to say “should I have been able to do all those things over US1?”
    emard
    @emard
    @sthornington if you have external ft2232 it is fastest and normally used as openocd jtag debugger for softcore cpus like litex or saxonsoc linux. Secondary US1 channel is possible and fully supported by openocd, but it will be unacceptably slow to transfer big files like kernel or root fs images. https://github.com/emard/ulx3s-jtagthru/blob/master/scripts/ft231x2.ocd here is some project that has openocd script to export secondard jtag channel to external pins but normally you can use it internally to soft-core too. See also the schematics for your board (v3.0.8) how FTDI is connected to FPGA
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab The address that is jumped to as soon as interrupts are enabled is $1140, which is the address that unused interrupt vectors are set to. So it is jumping to the wrong vector. I can't see why. The options seem to be that vpa_n is not set correctly, or the ipl pins are not set for long enough.
    Simon Thornington
    @sthornington
    @emard thanks, mostly what I want to get going is an on-board scope to dump traces, is there any particular recommended F2232 interface? Does that plug into the jtag header of the below the oled one?
    emard
    @emard
    any FT2232 breakout board or programmer is ok. It should connect to external pins GP/GN something, depends on where litex/saxonsoc expects them, usually pins 0-5 I guess. I does not plug to JTAG header, it doesn't need to program ECP5 but the CPU RISC5 done by FPGA. If you need onboard scope to display traces in realtime check hdl4fpga project, it has great scope for our boards.
    Simon Thornington
    @sthornington
    Yeah I saw that but is that not to make a scope for actual wires? I want a scope for on-chip/verilog wires
    Goran Mahovlic
    @goran-mahovlic
    As I know those wires are connected directly to FT2232 so you cannot scope then. @emard but maybe in future versions we could connect those two wires also on FPGA? So we could scope them? Maybe we can connect them over small jumpers, only for advanced users that would need two direct USB ports...
    Paul Ruiz
    @pnru_gitlab
    Having an onboard scope for fabric signals would be great, especially because in the Oberon cache I seem to have a hard to reconcile difference between simulated signals and observed behaviour. So far the only plan I could come up with was to route some signals to pins and use an external scope/analyzer. How fast could an on-board logic analyser be? For the problem at hand I'm looking at a ~100MHz signal.
    Paul Ruiz
    @pnru_gitlab

    @lawrie Yes, vpa_n could be the underlying issue. If the CPU does not recognise the autovector request, it would proceed as if a vector index was pushed on the databus -- which would be garbage in. Compare figure 5.6 and figure 6.4 in this doc: http://www.bitsavers.org/components/motorola/68000/MC68000_16-Bit_Microprocessor_Apr83.pdf

    However, I don't immediately see how your vpa_n code is wrong - so it may be something else still.

    Goran Mahovlic
    @goran-mahovlic
    For US2,US3,US4 you can scope USB signals - we are using ScopeIO for that
    But you cannot scope US1 as it is not connected directly to FPGA
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab @emard I think I have found the problem with interrupt processing with the Mac Plus. I had copied code from the QL which used a 68008 and had ipl0_n and ipl2_n tied together and not changed it. I will check if the SDRAM problem remains.
    emard
    @emard
    @sthornington @pnru_gitlab hdl4fpga/scopeio can scope any "wires" physical or internal. But it works only with diamond, vhdl usage is too advanced for ghdl. So your module to be debugged should be compiled with rest of hdl4fpga in order to be inspected. hdl4fpga is very small and efficient so compile time is very acceptable
    emard
    @emard
    Regarding clock rates to be scoped, it should run at SDRAM clock rate as the scopeio primary use was for debugging of RAM drivers :)