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    Lawrie Griffiths
    @lawrie
    @pnru_gitlab I added the esp32 spi ram interface and the SDRAM interface seems to be working:
    >>> print(''.join('{:02x}'.format(x) for x in osd.peek(0x64,4)))                                                                                      
    00401a42
    emard
    @emard
    Could it be that 68k has some bus protocol during interrupts that on the data and addr bus appear some data related to interrupt priority and it's source, which may be fooling sdram driver which is for example only tested to work with stable bus state and clean requests when RAM data perisist on bus all the time during the RAM cyclue
    Lawrie Griffiths
    @lawrie
    That might be the case, but I am now using BRAM for low ram addresses, which ought to fix that. So my current problem is that the level 1 (VIA) interrupt does not work. It gets stuck in the rom at address $1942, but I am pretty sure if shouldn't be there. I tried patching the level 1 interrupt routine at $1A42 to do an immediate RTE, but that makes no difference, suggesting that it is jumping somewhere else for the interrupt.
    emard
    @emard
    Oh we had some VIA blues from VIC20 too, was hard to fix, mostly analyzing the code and writing fake VIA which matched to existing keyboard scan routine :)
    Paul Ruiz
    @pnru_gitlab

    I think we may have two different errors here. The first is that the sdram read appears to malfunction immediately after an autovector cycle. This I can verify in simulation. My hypothesis is that in between the autovector bus cycle and the read bus cycle an sdram refresh cycle is started, which causes the sdram read cycle to start late and hence data to arrive too late. This hypothesis can also be checked by slowing down the CPU.

    The second is that the interrupt vector seems to be interpreted wrong, regardless of whether it is hardcoded in verilog, coming from sdram or block ram. Is it possible that the interrupt signal is withdrawn too early, and the CPU is taking the "spurious interrupt" vector instead?

    Lawrie Griffiths
    @lawrie
    I agree that it seems to be two errors.
    Lawrie Griffiths
    @lawrie
    I don't think the interrupt is withdrawn too soon. It needs to execute code to write to VIA registers to withdraw the interrupt.
    It looks a bit like the SCC interrupt is executed rather than the VIA one, as the code it gets stuck in is related to the SCC (serial chip).
    But i can't currently see how that could happen.
    The Mac has just the two interrupts, VIA (level 1) and SCC (level 2).
    Simon Thornington
    @sthornington
    @lawrie I never tried doing the debug bridge over US1, I figured it was hardwired to the FTDI which was being used to program and as a serial console for the SoC. Should I have been ableFwiw the main reason I am using LiteX is because the svd file helps write HAL layers in Rust more easily, I’m not particularly taken with nmigen.
    Hmm editing not working, wanted to say “should I have been able to do all those things over US1?”
    emard
    @emard
    @sthornington if you have external ft2232 it is fastest and normally used as openocd jtag debugger for softcore cpus like litex or saxonsoc linux. Secondary US1 channel is possible and fully supported by openocd, but it will be unacceptably slow to transfer big files like kernel or root fs images. https://github.com/emard/ulx3s-jtagthru/blob/master/scripts/ft231x2.ocd here is some project that has openocd script to export secondard jtag channel to external pins but normally you can use it internally to soft-core too. See also the schematics for your board (v3.0.8) how FTDI is connected to FPGA
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab The address that is jumped to as soon as interrupts are enabled is $1140, which is the address that unused interrupt vectors are set to. So it is jumping to the wrong vector. I can't see why. The options seem to be that vpa_n is not set correctly, or the ipl pins are not set for long enough.
    Simon Thornington
    @sthornington
    @emard thanks, mostly what I want to get going is an on-board scope to dump traces, is there any particular recommended F2232 interface? Does that plug into the jtag header of the below the oled one?
    emard
    @emard
    any FT2232 breakout board or programmer is ok. It should connect to external pins GP/GN something, depends on where litex/saxonsoc expects them, usually pins 0-5 I guess. I does not plug to JTAG header, it doesn't need to program ECP5 but the CPU RISC5 done by FPGA. If you need onboard scope to display traces in realtime check hdl4fpga project, it has great scope for our boards.
    Simon Thornington
    @sthornington
    Yeah I saw that but is that not to make a scope for actual wires? I want a scope for on-chip/verilog wires
    Goran Mahovlic
    @goran-mahovlic
    As I know those wires are connected directly to FT2232 so you cannot scope then. @emard but maybe in future versions we could connect those two wires also on FPGA? So we could scope them? Maybe we can connect them over small jumpers, only for advanced users that would need two direct USB ports...
    Paul Ruiz
    @pnru_gitlab
    Having an onboard scope for fabric signals would be great, especially because in the Oberon cache I seem to have a hard to reconcile difference between simulated signals and observed behaviour. So far the only plan I could come up with was to route some signals to pins and use an external scope/analyzer. How fast could an on-board logic analyser be? For the problem at hand I'm looking at a ~100MHz signal.
    Paul Ruiz
    @pnru_gitlab

    @lawrie Yes, vpa_n could be the underlying issue. If the CPU does not recognise the autovector request, it would proceed as if a vector index was pushed on the databus -- which would be garbage in. Compare figure 5.6 and figure 6.4 in this doc: http://www.bitsavers.org/components/motorola/68000/MC68000_16-Bit_Microprocessor_Apr83.pdf

    However, I don't immediately see how your vpa_n code is wrong - so it may be something else still.

    Goran Mahovlic
    @goran-mahovlic
    For US2,US3,US4 you can scope USB signals - we are using ScopeIO for that
    But you cannot scope US1 as it is not connected directly to FPGA
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab @emard I think I have found the problem with interrupt processing with the Mac Plus. I had copied code from the QL which used a 68008 and had ipl0_n and ipl2_n tied together and not changed it. I will check if the SDRAM problem remains.
    emard
    @emard
    @sthornington @pnru_gitlab hdl4fpga/scopeio can scope any "wires" physical or internal. But it works only with diamond, vhdl usage is too advanced for ghdl. So your module to be debugged should be compiled with rest of hdl4fpga in order to be inspected. hdl4fpga is very small and efficient so compile time is very acceptable
    emard
    @emard
    Regarding clock rates to be scoped, it should run at SDRAM clock rate as the scopeio primary use was for debugging of RAM drivers :)
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab I have switched back to using SDRAM for low ram addresses, and it now seems to be working. It is possible that the error I thought I had was due to me misinterpreting my diagnostics.
    Paul Ruiz
    @pnru_gitlab
    @lawrie excellent!
    Rob S
    @rob-ng15

    Hi all. Have been doing some more playing around with Silice by @sylefeb, a relatively easy to use HDL https://github.com/sylefeb/Silice and have implemented a Risc-V RVIMC CPU and plugged it into the display/audio system that I created for my j1eforth project. It is easier to write code in C for me than it is in Forth, so I've been able to implement an asteroids style game to test what I have been doing. Bound to be mistakes in there, doesn't yet fully meet timing, I'm working on it.

    Code at: https://github.com/rob-ng15/Silice-Playground/tree/master/risc-ice-v

    Asteroids game at: https://github.com/rob-ng15/Silice-Playground/blob/master/risc-ice-v/ULX3S/BUILD_ulx3s/Risc-ICE-V-Asteroids.bit

    Happy to take any suggestions! Not formally tested, other than it runs the compiled by GCC asteroids game.

    Lawrie Griffiths
    @lawrie
    Did you write the Risc-V processor from scratch or is it based on any other implementation?
    Rob S
    @rob-ng15
    I looked at Ice-V by @sylefeb to see what was involved and for how to implement the register files in BRAM, but written from scratch.
    emard
    @emard
    I have tried asterioids and I can say its one of the best and most playable :). Only the gun could be better, to fire bullets more often
    Rob S
    @rob-ng15
    Thanks for that. Appreciated! I'll have to free up some sprites to have more bullets. I'll see if I can speed the bullets up so that more can be fired.
    emard
    @emard
    Ahaaaa, its sprite number limit. Maybe bullets can be only a line drawn by head pixel and deleted by tail pixel (like stars background) but ok it's a silly suggestion, game is good
    Rob S
    @rob-ng15
    Thank you! I should be able to speed up the bullet, I'll have a look tomorrow. It takes a while to build, yosys takes a while!
    Simon Thornington
    @sthornington
    @emard very cool that scopeio can do internal wires, that's what I want. I will try it, but I have never used the diamond toolchain so that will take some work. I guess it also is too much for vhdl2verilog ? is there a build of diamond for osx ?
    emard
    @emard
    I have ready linux scripts so you just set path to diamond tools and type make, but for osx first diamond must be either installed or running in some vm
    Goran Mahovlic
    @goran-mahovlic
    we already have different version of diamond that runs inside docker
    I am using emard diamond makefile
    and this sudo xhost local:root export ETHMAC=xx:xx:xx:xx:xx:xx docker run -it --env="DISPLAY" --volume="/tmp/.X11-unix:/tmp/.X11-unix:rw" -v -v /localfolder/FPGA:/fpga -e LM_LICENSE_FILE=/fpga/license.dat --mac-address=$ETHMAC --privileged --ipc host -v /dev/bus/usb/:/dev/bus/usb/ dok3r/diamond:v3.7 export containerId=$(docker ps -l -q)
    xhost is only if I need GUI
    Goran Mahovlic
    @goran-mahovlic
    ETHMAC is MAC i have in dinamond license files that needs to be available
    Lawrie Griffiths
    @lawrie
    On my Mac Plus, it does not look too hard to get the keyboard working. I have hand-converted the Mister SystemVerilog PS/2 ketboard code that yosys did not handle. Getting the PS/2 mouse working looks a bit harder. Three of the mouse pins are connected to the VIA chip, and two to the Zilog SCC serial controller. I don't currently understand how it works. I am not that interested in implementing the serial ports yet, so I just want an SCC implementation that works for the mouse. However, I cannot use the keyboard and mouse until the OS is loaded, and I need floppy disk support for that.
    Lawrie Griffiths
    @lawrie
    On the Mac, the rom just contains start-up code and device drivers. On the QL, it contained the whole operating system. The biggest part of Mac Plus rom seems to be the file system implementation.
    emard
    @emard
    I had similar situation with ORAO, system works up to some point but no tape loading. Then I used emulator to create RAM image, patched ROM to restore registers and jump to image. Could get some early results maybe
    Rob S
    @rob-ng15
    @emard, I've made changes to the asteroids game for you, the bullets are faster now, but so are those from the UFO! Uploaded onto github.
    emard
    @emard
    @rob-ng15 That's it! bullets fly well now! Can you also make 12F version, it if fits?
    Rob S
    @rob-ng15
    I don't know what changes will be required, but it uses 96% of the block ram, so possibly too big?
    emard
    @emard
    OK, then it's too big, don't optimize. I thought only to replace 85F with 12F and try to compile and if it doesn't fit, that's the reason why 85F is better :)