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    Lawrie Griffiths
    @lawrie
    I was missing the assigns.
    emard
    @emard
    it can be shorted as wire clkdvi = clocks[0] and delete wire declaration above...
    Lawrie Griffiths
    @lawrie
    It is working now.
    emard
    @emard
    ecppack --compress can also be added
    Lawrie Griffiths
    @lawrie
    Yes, I have done that and removed idcode.
    I have pushed it now. I will see if I can get zx81 mode working.
    emard
    @emard
    Im compiling current version
    it works great, picture stable
    Lawrie Griffiths
    @lawrie
    My capture device still does not like the picture and the monitor reports it as 57Hz.
    But it is stable on my monitor.
    emard
    @emard
    I found out that I have to be close to some standard pixel clocks and refresh rates, eg if I get 25MHz +- 0.3 MHz and 60Hz +- 0.3 Hz then nobody complains
    Lawrie Griffiths
    @lawrie
    I think ZX81 mode does work but the keyboard is mapped differently and the shift key seems to work differently. It is a toggle like caps lock. Not sure if that is correct.
    emard
    @emard
    Can there be some toplevel option like parameter zx=80 or zx=81 or similar to select which machine is emulated
    I have been trying for some time to make ST7789 display apple ][ video. Currently I have some early results, it was nasty because of their custom video format
    Lawrie Griffiths
    @lawrie
    zx81 is currently a register set to 0 or 1. I will probably make it a parameter. Perhaps sometime we should support options in the OSD. That is how Mist and Mister select such things.
    I need to add tape loading before it is worth adding an OSD to the ZX80/81.
    emard
    @emard
    We can support OSD for some file loading directly to memory. If tape is distributed in modern form as real bytes that get to RAM, then this can be parsed, RAM updated and few basic pointers adjusted. If there's some copy protection multi-part tapes, then it's not so easy and tape loading must be supported
    emard
    @emard
    https://github.com/emard/apple2fpga I finally got the sucker working. LCD ST7789 displays screen correctly now
    emard
    @emard
    wait I think still something is not ok as commited
    emard
    @emard
    I think now it works ok for LCD. osd disk2.py has still some bugs. OSD works but if both up/down buttons are pressed sometimes it stops responding. I should fix it by taking code from mac128
    AndrewCapon
    @AndrewCapon
    Hi Guys, I have junked all the stuff I was doing before with SaxonSoc and got the dev-0.2 branch again. I thought I would build the linux version by following : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.2/bsp/radiona/ulx3s/smp/README.md I'm running into issues with SBT/Scala though:
    [error] sbt.librarymanagement.ResolveException: Error downloading org.scalameta:semanticdb-scalac_2.12.10:4.1.0
    Anyone any ideas on this?
    Lawrie Griffiths
    @lawrie
    I built that without problems. I have not seen that error, perhaps @Dolu1990 has.
    Dolu1990
    @Dolu1990

    Error downloading org.scalameta:semanticdb-scalac_2.12.10:4.1.0

    Didn't had that, seems like some SBT depedancies or something like this broke

    will try one thing
    @AndrewCapon What does sbt --version give you ?
    Dolu1990
    @Dolu1990
    Also sometime it happend that some stuff out there is the wild web break for some time before comming back XD
    (Might be self resolved now)
    AndrewCapon
    @AndrewCapon
    MP12:SaxonSoc andrewcapon$ sbt --version sbt version in this project: 1.3.13 sbt script version: 1.4.5
    It works fine in the dev branch
    And is now working fine in the dev-02 branch!
    Bloody computers
    AndrewCapon
    @AndrewCapon
    Thanks for the pointers :)
    Dolu1990
    @Dolu1990
    XD
    no worries
    That's quite a frustrating things, especialy it also happen sometime in automatic regressions in travis
    AndrewCapon
    @AndrewCapon

    Hi Guys,

    I’m fumbling around in the dark here trying to get interrupts going in a minimal SaxonSoc, just simply a timer interrupt to begin with.

    I have been looking around the scala code with little understanding but I’m guessing I need a BmbPlicGenerator and a BmbClintGenerator but am very confused about how I connect these up.

    I can see in the clusterGenerator:

     val cores = for(cpuId <- 0 until cpuCount) yield {
        val vex = VexRiscvBmbGenerator()
        vex.setTimerInterrupt(clint.timerInterrupt(cpuId))
        vex.setSoftwareInterrupt(clint.softwareInterrupt(cpuId))
        plic.addTarget(vex.externalInterrupt)
        plic.addTarget(vex.externalSupervisorInterrupt)
        List(clint.logic, vex.logic).produce{
          for (plugin <- vex.config.plugins) plugin match {
            case plugin : CsrPlugin if plugin.utime != null => plugin.utime := RegNext(clint.logic.io.time)
            case _ =>
          }
        }
        vex
      }

    And have done a copy/paste/change to a single core/hope, but I am a bit confused how this all gets added to the interconnect.

    Has anyone done this or has some info about how to?

    emard
    @emard
    I also need assistance, for ghdl I often get unlocated error. Does somebody know which source pattern causes this so I can easily find what to fix
    ERROR: wire not found for $posedge
    AndrewCapon
    @AndrewCapon
    I managed to get an Apb3MachineTimerGenerator going instead of the clint, would still be intereseted in how clint is meant to be connected up though
    Lawrie Griffiths
    @lawrie
    @AndrewCapon You would be better off asking these questions on the Vexriscv gitter as @Dolu1990 responds to that frequently, but usually only responds here when pinged. I think I am the only one on this forum that has worked with the scala source of SaxonSoc, and I am not very active on it right now.
    AndrewCapon
    @AndrewCapon
    Thanks @lawrie, will do that...
    Dolu1990
    @Dolu1990
    @AndrewCapon Basicaly, when there is a implicit https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/scala/saxon/VexRiscvClusterGenerator.scala#L18 defined, peripherals will by default be mapped on that bus. via
    https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/scala/saxon/BmbPeripheralGenerator.scala#L199 (BmbImplicitPeripheralDecoder)
    All those connections can be specified manualy/overrided
    Lawrie Griffiths
    @lawrie
    I have started a Verilog implementation of the Raspberry Pi RP2040 PIO protocol. PIO allows use to write small assembler programs that implement any pin protocol on any gpio pins at full speed without involving the CPU. My implementation is simulation only and incomplete at the moment - https://github.com/lawrie/fpga_pio
    Any self-respecting SoC should have a PIO implementation.
    AndrewCapon
    @AndrewCapon

    @AndrewCapon Basicaly, when there is a implicit...

    Nice thanks for the info, will look at that...

    Rob S
    @rob-ng15

    Hi all, been doing some work on my Risc-V system (now called PAWS). I've added in the option of a second CPU thread, based on the idea of SMT. Have created a modifed version of my asteroids game that uses the second thread to control the asteroids as a proof of concept. Done a fair bit of tweaking to my 3dmaze game, the most upto date is the one called maze-abstractaccess.c compiled to 3DMAZE-2.PAW

    https://github.com/rob-ng15/Silice-Playground/tree/master/PAWS

    splinedrive
    @splinedrive
    Hi, I have a question I was able to learn from fpg4fun and some other implementation to write a primitiv sdram controller on my own. I don't understand why such controller is not implemented directly on a sdram chip? A primitiv implementation costs a small statemachine with a few states. I know you can burst, interleave and whatever. But I don't understand it!
    emard
    @emard
    @splinedrive there exist "pseudo"-SRAM chips they internally have SDRAM and the controller you need and externally present them as SRAM. However, effective bandwidth which can be achieved from such SRAM chip is much less than with bare SDRAM because on specific application with cache or cpu signaling features one can do better transfer rate with dedicated controller, that's why in FPGA there are plently of different SDRAM drivers.