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    Dolu1990
    @Dolu1990
    XD
    no worries
    That's quite a frustrating things, especialy it also happen sometime in automatic regressions in travis
    AndrewCapon
    @AndrewCapon

    Hi Guys,

    I’m fumbling around in the dark here trying to get interrupts going in a minimal SaxonSoc, just simply a timer interrupt to begin with.

    I have been looking around the scala code with little understanding but I’m guessing I need a BmbPlicGenerator and a BmbClintGenerator but am very confused about how I connect these up.

    I can see in the clusterGenerator:

     val cores = for(cpuId <- 0 until cpuCount) yield {
        val vex = VexRiscvBmbGenerator()
        vex.setTimerInterrupt(clint.timerInterrupt(cpuId))
        vex.setSoftwareInterrupt(clint.softwareInterrupt(cpuId))
        plic.addTarget(vex.externalInterrupt)
        plic.addTarget(vex.externalSupervisorInterrupt)
        List(clint.logic, vex.logic).produce{
          for (plugin <- vex.config.plugins) plugin match {
            case plugin : CsrPlugin if plugin.utime != null => plugin.utime := RegNext(clint.logic.io.time)
            case _ =>
          }
        }
        vex
      }

    And have done a copy/paste/change to a single core/hope, but I am a bit confused how this all gets added to the interconnect.

    Has anyone done this or has some info about how to?

    emard
    @emard
    I also need assistance, for ghdl I often get unlocated error. Does somebody know which source pattern causes this so I can easily find what to fix
    ERROR: wire not found for $posedge
    AndrewCapon
    @AndrewCapon
    I managed to get an Apb3MachineTimerGenerator going instead of the clint, would still be intereseted in how clint is meant to be connected up though
    Lawrie Griffiths
    @lawrie
    @AndrewCapon You would be better off asking these questions on the Vexriscv gitter as @Dolu1990 responds to that frequently, but usually only responds here when pinged. I think I am the only one on this forum that has worked with the scala source of SaxonSoc, and I am not very active on it right now.
    AndrewCapon
    @AndrewCapon
    Thanks @lawrie, will do that...
    Dolu1990
    @Dolu1990
    @AndrewCapon Basicaly, when there is a implicit https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/scala/saxon/VexRiscvClusterGenerator.scala#L18 defined, peripherals will by default be mapped on that bus. via
    https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/hardware/scala/saxon/BmbPeripheralGenerator.scala#L199 (BmbImplicitPeripheralDecoder)
    All those connections can be specified manualy/overrided
    Lawrie Griffiths
    @lawrie
    I have started a Verilog implementation of the Raspberry Pi RP2040 PIO protocol. PIO allows use to write small assembler programs that implement any pin protocol on any gpio pins at full speed without involving the CPU. My implementation is simulation only and incomplete at the moment - https://github.com/lawrie/fpga_pio
    Any self-respecting SoC should have a PIO implementation.
    AndrewCapon
    @AndrewCapon

    @AndrewCapon Basicaly, when there is a implicit...

    Nice thanks for the info, will look at that...

    Rob S
    @rob-ng15

    Hi all, been doing some work on my Risc-V system (now called PAWS). I've added in the option of a second CPU thread, based on the idea of SMT. Have created a modifed version of my asteroids game that uses the second thread to control the asteroids as a proof of concept. Done a fair bit of tweaking to my 3dmaze game, the most upto date is the one called maze-abstractaccess.c compiled to 3DMAZE-2.PAW

    https://github.com/rob-ng15/Silice-Playground/tree/master/PAWS

    splinedrive
    @splinedrive
    Hi, I have a question I was able to learn from fpg4fun and some other implementation to write a primitiv sdram controller on my own. I don't understand why such controller is not implemented directly on a sdram chip? A primitiv implementation costs a small statemachine with a few states. I know you can burst, interleave and whatever. But I don't understand it!
    emard
    @emard
    @splinedrive there exist "pseudo"-SRAM chips they internally have SDRAM and the controller you need and externally present them as SRAM. However, effective bandwidth which can be achieved from such SRAM chip is much less than with bare SDRAM because on specific application with cache or cpu signaling features one can do better transfer rate with dedicated controller, that's why in FPGA there are plently of different SDRAM drivers.
    emard
    @emard
    @rob-ng15 I have tried your PAWS, it first checks SDRAM and then asks to insert FAT16 SDRAM card. I have some 8GB card that is I think FAT32, esp32 can R/W it normally. Is it really true FAT16 needed or something else? For example for SD card and SPI flash, they are quad-SPI capable but if used as SPI 1-bit then other pins should be driven 1
    Oh yes I have besides primary fat partition, also other partitions on SD card with linux and oberon stuff, it may also appear strange for some fat drivers...
    splinedrive
    @splinedrive
    @emard thanks I see. It is really fun a SDRAM controller. I suppose on my anlogic fpga board (Sipeed Tang) is PSRAM. But I tried this board only once uploading a bitstream was horrible slow.
    It is possible to speedup yosys nextpnr with a make -j $(nproc)? I tried it doesn't work - maybe it is not possible.
    emard
    @emard
    WIth presumption it's SDRAM inside of PSRAM (honoring RAS/CAS timings and preventing original refresh by e.g. driving undocumented state of CS UBL LBL pins and doing custom refresh) it can be driven almost as fast as SDRAM but its very hackish approach
    splinedrive
    @splinedrive
    :)
    emard
    @emard
    At ULX2S board, vendor changed specs of PSRAM's and refresh was effectively disabled by PCB connection of CSn tied to GND. 250 boards produced, candidates to trash. so collegue Marko Zec fixed them by finding out this interesting PSRAM features :). He cursed vendors and their specs long time thereafter and promised never again to use PSRAM's :)
    splinedrive
    @splinedrive
    Wow! What is your opinion about hyperram?
    emard
    @emard
    I won't recommend it if you have enough FPGA pins. For lower pin count it requires double frequency, 333 MHz instead of 166 MHz. FPGA has difficulty with every larger core above 200MHz so going low freq relaxes complex design to synthesize easier.
    Second issue is production related. There is single chip vendor of hyperram. SDRAMs pin compatibles one can buy any time from various vendors. Production of hyperram boards can be delayed because of manufacturer lead times...
    splinedrive
    @splinedrive
    @emard Is interessting to understand the view of a board manufacture.I bought 256Mbit from 1BitSquared and wanted to play with it :) I like that pmod.
    emard
    @emard
    If you already have PMOD, this is cool item to experiment. It's very handy when you have big project for hyperram (maybe this https://mega65.org/ but it's really huge :-) . then it's much easier to just plug hyperram hardware instead of porting to another RAM chip
    splinedrive
    @splinedrive
    :)
    emard
    @emard
    I actually found that hyperram is now produced by 3 vendors, Cypress original, ISSI and Winbond. There is no 256Mbit on mouser. 128Mbit exists but stock is rather small, about 200-300 pcs total in mouser stock
    splinedrive
    @splinedrive
    The pmod 256Mbit uses 4x64 chips from spansion (cypress). https://1bitsquared.com/products/pmod-hyperram
    emard
    @emard
    ahaaa, so it makes 32MB total. The data pin bus is un-tidy, I would expect one PMOD 8-pin has D0-D7, the other PMOD 8-pin signaling, not the mix :) my wish for v2.0 hyperram :)
    Rob S
    @rob-ng15
    @emard It does have to be FAT16 at present as I had to quickly write my own file system reader.
    Rob S
    @rob-ng15
    I have to rely on what is provided in Silice at present.
    liebman
    @liebman
    Whats the minimum needed in order to effect a passthru for programming the esp32? I want to create seperate component to instantiate in my projects so at least during development I can easially re-flash the esp32 without disrupting whatever I have on the fpga at the time.
    Lawrie Griffiths
    @lawrie
    You need:
    assign wifi_rxd = ftdi_txd;
    assign ftdi_rxd = wifi_txd;
    But you can't do that if your project uses a uart interface to the host.
    emard
    @emard
    @liebman above is not enough as passthru for esp32 programming, it is just for serial console. I should review my project for passthru and make it reliably synthesize with yosys and clean it up from spi oled bnts etc what is current passthru that is in vhdl and compiles with diamond
    esp32 needs handling GPIO0 and GPIO2, EN I think with rs232 signaling rts dtr something
    fpga core has to simulate behavor of 2 BJT transistors found on usualy esp32 module. time-response of this logical circuit must be very fast
    liebman
    @liebman
    I think this (and the btn could be eliminated):
      -- TX/RX passthru
      ftdi_rxd <= wifi_txd;
      wifi_rxd <= ftdi_txd;
    
      -- Programming logic
      -- SERIAL  ->  ESP32
      -- DTR RTS -> EN IO0
      --  1   1     1   1
      --  0   0     1   1
      --  1   0     0   1
      --  0   1     1   0
      S_prog_in(1) <= ftdi_ndtr;
      S_prog_in(0) <= ftdi_nrts;
      S_prog_out <= "01" when S_prog_in = "10" else
                    "10" when S_prog_in = "01" else
                    "11";
      wifi_en <= S_prog_out(1);
      wifi_gpio0 <= S_prog_out(0) and btn(0); -- holding BTN0 will hold gpio0 LOW, signal for ESP32 to take control
    Irvise
    @irvise:matrix.org
    [m]
    Quick question. Has anybody here ran the Microwatt POWER CPU?
    Y just watched the Australian linux conf and in the Microwatt slides they say it has support for the ULX3S
    However, about a month ago I did not find anything related to that in their github
    liebman
    @liebman
    @emard this seems to work well
    module ulx3s_passthru (
      input  wire txd,
      output wire rxd,
      input  wire dtr,
      input  wire rts,
      input  wire esp_txd,
      output wire esp_rxd,
      output wire esp_en,
      output wire esp_io0,
    );
      // TX/RX passthru
      assign rxd     = esp_txd;
      assign esp_rxd = txd;
    
      // Programming logic
      // SERIAL  ->  ESP32
      // DTR RTS -> EN IO0
      //  1   1     1   1
      //  0   0     1   1
      //  1   0     0   1
      //  0   1     1   0
      assign esp_en  = ~( dtr & ~rts);
      assign esp_io0 = ~(~dtr &  rts);
    
    endmodule
    liebman
    @liebman
    This is a little cleaner
      assign esp_en  = ~dtr |  rts;
      assign esp_io0 =  dtr | ~rts;
    emard
    @emard
    @liebman hey great work, let me try this and I can add to ulx3s-misc examples :)
    emard
    @emard
    @irvise:matrix.org I know our board mentioned as supported on github https://github.com/antonblanchard/chiselwatt but I myself haven't tried it, but using chisel for code generation it should build straightforward make ECP5_BOARD=ulx3s synth
    liebman
    @liebman

    @emard this one is improved. It tristates gpio0 instead if setting it high so that it can be used elsewhere if needed. Also added an enable that can be used as a reset for the esp32.

    module ulx3s_passthru (
      input  wire txd,
      output wire rxd,
      input  wire dtr,
      input  wire rts,
      input  wire esp_txd,
      output wire esp_rxd,
      output wire esp_en,
      output wire esp_io0,
      input  wire en,
    );
      // TX/RX passthru
      assign rxd     = esp_txd;
      assign esp_rxd = txd;
    
      // Programming logic
      // SERIAL  ->  ESP32
      // DTR RTS -> EN IO0
      //  1   1     1   Z
      //  0   0     1   Z
      //  1   0     0   Z
      //  0   1     1   0
      assign esp_en  = (~dtr |  rts) & en;
      assign esp_io0 = ( dtr | ~rts) ? 1'bz : 1'b0; // we only want to drive this pin low
    
    endmodule

    can be called like

    module top(
        input wire clk_25mhz,
        output wire ftdi_rxd,
        input wire ftdi_txd,
        inout wire ftdi_ndtr,
        inout wire ftdi_nrts,
        output wire wifi_rxd,
        input wire wifi_txd,
        inout wire wifi_en,
        inout wire wifi_gpio0,
        output [7:0] led,
        input  [6:0] btn,
        output wire shutdown,
    );
        ulx3s_passthru passthru(.txd(ftdi_txd),
                                .rxd(ftdi_rxd),
                                .dtr(ftdi_ndtr),
                                .rts(ftdi_nrts),
                                .esp_txd(wifi_txd),
                                .esp_rxd(wifi_rxd),
                                .esp_en(wifi_en),
                                .esp_io0(wifi_gpio0),
                                .en(btn[0]),  // btn[0] will work as a reset for esp
        );
    
        // blinky for something to do so we know its operational
        assign led[0]   = btn[1];
        assign led[6:1] = 0;
        assign led[7]   = wifi_gpio0;
    endmodule