@emard this one is improved. It tristates gpio0 instead if setting it high so that it can be used elsewhere if needed. Also added an enable that can be used as a reset for the esp32.
module ulx3s_passthru (
input wire txd,
output wire rxd,
input wire dtr,
input wire rts,
input wire esp_txd,
output wire esp_rxd,
output wire esp_en,
output wire esp_io0,
input wire en,
);
// TX/RX passthru
assign rxd = esp_txd;
assign esp_rxd = txd;
// Programming logic
// SERIAL -> ESP32
// DTR RTS -> EN IO0
// 1 1 1 Z
// 0 0 1 Z
// 1 0 0 Z
// 0 1 1 0
assign esp_en = (~dtr | rts) & en;
assign esp_io0 = ( dtr | ~rts) ? 1'bz : 1'b0; // we only want to drive this pin low
endmodule
can be called like
module top(
input wire clk_25mhz,
output wire ftdi_rxd,
input wire ftdi_txd,
inout wire ftdi_ndtr,
inout wire ftdi_nrts,
output wire wifi_rxd,
input wire wifi_txd,
inout wire wifi_en,
inout wire wifi_gpio0,
output [7:0] led,
input [6:0] btn,
output wire shutdown,
);
ulx3s_passthru passthru(.txd(ftdi_txd),
.rxd(ftdi_rxd),
.dtr(ftdi_ndtr),
.rts(ftdi_nrts),
.esp_txd(wifi_txd),
.esp_rxd(wifi_rxd),
.esp_en(wifi_en),
.esp_io0(wifi_gpio0),
.en(btn[0]), // btn[0] will work as a reset for esp
);
// blinky for something to do so we know its operational
assign led[0] = btn[1];
assign led[6:1] = 0;
assign led[7] = wifi_gpio0;
endmodule
assign led[7] = wifi_gpio0;
PCLK
?
~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v
%Warning-WIDTH: my_tx_uart.v:17: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's RTOIS generates 32 bits.
: ... In instance my_tx_uart
localparam CYCLES_PER_SYMBOL = $rtoi(SYSTEM_CYCLES/BAUDRATE);
^~~~~~~~~~~~~~~~~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
wait_states <= CYCLES_PER_SYMBOL;
return_state <= 1;
state <= 7;
localparam real re_somethng = 3.14;
localparam integer int_something = re_something;
wire [31:0] wire_something = int_something;
localparam [WAITSTATES_BIT_WIDTH-1:0] CYCLES_PER_SYMBOL = (WAITSTATES_BIT_WIDTH)'($rtoi(SYSTEM_CYCLES/BAUDRATE));
~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v
~/my_verilog/my_uart $