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    liebman
    @liebman
    I want to be able to reset the esp32 from one of the buttons (or even have the FPGA do it) without disterbing what Im setting up in the FPGA.
    @emard do any of the example have esp32 read from FPGA via SPI?
    emard
    @emard
    Yes a lot, we use osd.py in all our retrogaming stuff. FPGA implements SPI slave emulator of something similar to SPI RAM chip, ESP32 is SPI master. There is gpio0 interrupt line from FPGA to ESP32 when FPGA (as slave) must initiate some SPI actions from ESP32.
    emard
    @emard
    You can take my ulx3s_c64 as example which is a bit shorter and cleaner than others. SPI slave stuff is actually verilog with vhdl wrappers. The mostly same code is also in https://github.com/emard/ulx3s-misc/tree/master/examples/dvi_osd/hdl - it implements BTNs interrupts and esp32 osd.py drive some SD card file selector
    liebman
    @liebman
    I’ll take a look - thanks
    emard
    @emard
    One drawback is that in current ulx3s boards there is no clock capable pins from esp32 to fpga, so SPI is scanned with clock and effective SPI max speed is cca clock_freq/5
    liebman
    @liebman
    thats good to know, which are the (non esp) pins that are clock capable?
    (that explains why some of my tests failed)
    emard
    @emard
    They are mentioned on pdf schematics_v3.0.8 let me see
    https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf page 2 GP,GN 12 are clock capable and shared with ESP32 but small design fail is those pins are on ESP32 input only. In new board v3.1.5 I tried to fix this by routing one esp32 output capable pin to FPGA clock input capable...
    New board is just drawing, not yet produced :)
    liebman
    @liebman
    What on the schematic denotes clock capable?
    PCLK?
    emard
    @emard
    PCLK .. means primary clock capable pins. they are best. GR_PCLK are second best, general routed to primary clock capable
    emard
    @emard
    A small fix could be possible with a jumper GN11-GN12 this will connect ESP32 pin 25 GN11 which is output capable to FPGA clock input capable at GN12
    Dave Anderson
    @danderson
    Hi, is there reference documentation for the format of the LPF files somewhere?
    Dave Anderson
    @danderson
    Couldn't find any decent docs other than nextpnr source code and poorly explained technical notes from lattice, so I wrote https://github.com/danderson/ulxs/blob/main/lpf.md
    Also comes with pointers to the Lattice tech notes that go into more detail about e.g. ECP5 configuration and I/O pin config.
    e2kgh
    @e2kgh
    @danderson : Excellent job, describing the LPF format!!! Just one small remark, when you describe the "signal name", please add, that it should be exactly the same name as in top level HDL, including upper/lower case letters. It bites me all the times, when I move between tools, some don't care, some do, and the error messages are not always meaningful ;-) THANKS AGAIN!
    emard
    @emard
    @danderson I have common problem most often with gp/gn pins. For simplicity I use as gp[27:0] but when they need to be 3-state and some pins IN, some OUT, then problems comes with yosys or ghdl. I still don't know how exactly opensource compilers interpret mixed directions, but often I have to change LPF instead of [] to define gp0, gp1, gp2 and specify each as input/output at toplevel, than things start to work. So I'm thinking first to double each LPF line, one for gp[0] and gp0. I don't know is there some better way to make them individually defined as gp0, gp1, ... and then make gp[27:0] bus out components gp0, gp1, ... without 2x repeating same BGA pin each time...
    Dave Anderson
    @danderson
    @emard hmm, that's useful info, thanks. Looking at the top-level HDL, I guess arrays can't be arbitrary direction per-bit, it's either all in, all out, or all bidirectional... So then by the time you get to nextpnr routing, it's too late to say "lol jk these pins are different"
    maybe the best way to go is to have a configuration utility to generate LPF files for individual projects... That way we can read the HDL ports and map them instead of having to guess the right config...
    Dave Anderson
    @danderson
    @e2kgh I added a section about signal names to clarify that (hopefully :) )
    splinedrive
    @splinedrive
    Hi, does someone know howto configure the olimex hx80k evb without flashing the flash? Do I have to use the jtag pins on the board? I have not seen any documentation about it. Does someone experience with it? :) thanx
    emard
    @emard
    I don't know much but if it is ice40 board, it has SPI config and not JTAG. RPI >= 2 for example can be directly connected to this SPI and program ice40.
    splinedrive
    @splinedrive
    @emard Thanks for your hint. Yes it is possible, I have seen it in the schematic https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/HARDWARE/REV-B/iCE40HX8K-EVB_Rev_B.pdf there is also a note 2. If you want to use cram, you have to umount R9 and populate R19. Good to know. flashing is too slow.
    These resistors are to small for me :(. Don't know why they put no jumpers on to it.
    emard
    @emard
    Get soldering wick wire, quality flux, 0.3mm solder wire, food-grade ethanol 96%, magnifying glass 10x, good illumination and enough time. Do not apply force if R sticks, traces easily detach from PCB. Let it cool and flux and wick again to remove solder. Clean with ethanol and optionally drink some to relax :)
    splinedrive
    @splinedrive
    @emard thanks I must order some parts. But I will try :). Or I have to find out howto use JTAG with olimex. I always used ftdi based fpgas and this is very easy!
    emard
    @emard
    ftdi based jtag should also be able to talk spi too if you have adequate programming software.
    I have tried RPI to program ice40 and it was good and fast, all software ready there
    splinedrive
    @splinedrive
    I have a ft232h breakout board here I will try this with openbcd. I got headache from the olimex.
    emard
    @emard
    try also https://github.com/trabucayre/openFPGALoader it lists iCE40-HX8K and ft232h support but I never tried
    splinedrive
    @splinedrive
    I will try after work! :)
    e2kgh
    @e2kgh
    @emard: where is the "RPI to program ice40"?
    splinedrive
    @splinedrive
    @e2kgh https://www.olimex.com/wiki/ICE40HX1K-EVB#Iceprog_with_Raspberry_PI iceprog over rpi header. Or you have a icoboard you are able to mount on a rpi. http://icoboard.org/
    splinedrive
    @splinedrive
    Any idea howto bring a localparamter value to a fix bit witdh?
    ~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v
    %Warning-WIDTH: my_tx_uart.v:17: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's RTOIS generates 32 bits.
                                   : ... In instance my_tx_uart
    localparam CYCLES_PER_SYMBOL = $rtoi(SYSTEM_CYCLES/BAUDRATE);
               ^~~~~~~~~~~~~~~~~
                    ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
    %Error: Exiting due to 1 warning(s)
    Because I use this in my statemachine but I would like to remove this warning!
        wait_states <= CYCLES_PER_SYMBOL;
        return_state <= 1;
        state <= 7;
    Lawrie Griffiths
    @lawrie
    I believe you can specify a width on localparam, e.g. localparam [24:0] CYCLES_PER_SECOND = ....
    emard
    @emard
    rtoi is not portable to diamond. It can probably be made like
    localparam real re_somethng = 3.14;
    localparam integer int_something = re_something;
    wire [31:0] wire_something = int_something;
    splinedrive
    @splinedrive
    @lawrie @emard Thanks. I have tried this and verilator is warning free:
    localparam [WAITSTATES_BIT_WIDTH-1:0] CYCLES_PER_SYMBOL = (WAITSTATES_BIT_WIDTH)'($rtoi(SYSTEM_CYCLES/BAUDRATE));
    
    ~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v
    ~/my_verilog/my_uart $
    splinedrive
    @splinedrive

    @lawrie @emard The problem of my solution is. It is SystemVerilog :(. @emard yours is portable but produces the same warnings. @lawrie your solution produces the same warnings. I have downloaded ieee standard and found nothing. When I do

     verilator --language 1364-2005 -Wall --lint-only --top-module my_rx_uart my_rx_uart.v

    I get with []'() an error, because verilog 2005 doesn't support this syntax. verilator operates default with SystemVerilog. And when I remove []`(), verilog 2005 will produces the same warning again:

    %Warning-WIDTH: my_tx_uart.v:19: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's VARREF 'x' generates 32 bits.
                                   : ... In instance my_tx_uart

    Any idea? If not I will switch to SystemVerilog :)

    Lawrie Griffiths
    @lawrie
    The syntax seems to be supported by yosys without having to specify SystemVerilog. What you do probably depends on which tools you want to use.
    splinedrive
    @splinedrive
    :)
    splinedrive
    @splinedrive
    It is crazy the uart works with long cables with 2MBaud :). Why everbody is using 9600 Baud? I have done loopback without FIFO :)
    always @(posedge clk) begin
        if (tx_ready) begin
            transfer <= rx_valid;
            tx_data <= rx_data;
        end
    end
    emard
    @emard
    UART works up to 3Mbaud (3000000 bps). Expect few errors, any simple block retry and crc will make it error-free.
    splinedrive
    @splinedrive
    @emard Yesterday night I tried 3MBaud with 50MHz internal clock. Without any error correction. I generated 318M random data from /dev/urandom. And made a loopback without any correction and I got no errors - I check it with md5sum. I was surprised :)
    cat data.bin > /dev/ttyUSB0
    cat /dev/ttyUSB0 > data_loopback.bin
    $ du -hs data*
    318M    data.bin
    318M    data_loopback.bin
    
     $ stty -F /dev/ttyUSB2
    speed 3000000 baud; line = 0;
    min = 1; time = 0;
    -brkint -icrnl -imaxbel
    -opost
    -isig -icanon -echo
    $ md5sum data_loopback.bin data.bin
    7ff679bc7934c886a7545af78b56ea28  data_loopback.bin
    7ff679bc7934c886a7545af78b56ea28  data.bin
     $
    emard
    @emard
    Lucky you, there is some project with hdl4fpga that uploads picture to framebuffer and it requires block&crc. It could be that loopback to itself runs 100% OK but if it needs to take data at independenty clocked receiver, we experience some error every 20-100KB
    e2kgh
    @e2kgh
    Exactly, you are running on the same clock, so actually you could skip all the features, an real UART has ;-)