~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v %Warning-WIDTH: my_tx_uart.v:17: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's RTOIS generates 32 bits. : ... In instance my_tx_uart localparam CYCLES_PER_SYMBOL = $rtoi(SYSTEM_CYCLES/BAUDRATE); ^~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to 1 warning(s)
wait_states <= CYCLES_PER_SYMBOL; return_state <= 1; state <= 7;
localparam real re_somethng = 3.14; localparam integer int_something = re_something; wire [31:0] wire_something = int_something;
localparam [WAITSTATES_BIT_WIDTH-1:0] CYCLES_PER_SYMBOL = (WAITSTATES_BIT_WIDTH)'($rtoi(SYSTEM_CYCLES/BAUDRATE)); ~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v ~/my_verilog/my_uart $
@lawrie @emard The problem of my solution is. It is SystemVerilog :(. @emard yours is portable but produces the same warnings. @lawrie your solution produces the same warnings. I have downloaded ieee standard and found nothing. When I do
verilator --language 1364-2005 -Wall --lint-only --top-module my_rx_uart my_rx_uart.v
I get with '() an error, because verilog 2005 doesn't support this syntax. verilator operates default with SystemVerilog. And when I remove `(), verilog 2005 will produces the same warning again:
%Warning-WIDTH: my_tx_uart.v:19: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's VARREF 'x' generates 32 bits. : ... In instance my_tx_uart
Any idea? If not I will switch to SystemVerilog :)
cat data.bin > /dev/ttyUSB0 cat /dev/ttyUSB0 > data_loopback.bin
$ du -hs data* 318M data.bin 318M data_loopback.bin $ stty -F /dev/ttyUSB2 speed 3000000 baud; line = 0; min = 1; time = 0; -brkint -icrnl -imaxbel -opost -isig -icanon -echo
$ md5sum data_loopback.bin data.bin 7ff679bc7934c886a7545af78b56ea28 data_loopback.bin 7ff679bc7934c886a7545af78b56ea28 data.bin $
.program uart_tx .side_set 1 opt pull block side 1 set x 7 side 0  again: out pins 1 jmp x-- again 
~/hacking/ulx3s/fpga_pio $ git pull remote: Enumerating objects: 55, done. remote: Counting objects: 100% (55/55), done. remote: Compressing objects: 100% (26/26), done. remote: Total 109 (delta 36), reused 44 (delta 27), pack-reused 54 Receiving objects: 100% (109/109), 29.51 KiB | 332.00 KiB/s, done. Resolving deltas: 100% (64/64), completed with 11 local objects. From github.com:lawrie/fpga_pio fcd4f20..6648b49 main -> origin/main Updating fcd4f20..6648b49 Fast-forward README.md | 104 ++++++++- asm/copybit.asm | 4 + asm/pwm.asm | 1 - blackicemx/Makefile | 2 +- blackicemx/pio.pcf | 2 + sim/copybit.mem | 2 + sim/copybit.v | 129 ++++++++++
@emard Good point! I have read something about audio in HDMI standard https://ez.analog.com/cfs-file/__key/telligent-evolution-components-attachments/00-317-00-00-00-05-21-37/HDMISpecification13a.pdf . The point is we have a dvi implementation and hdmi needs E-EDDID Data Structure. You can read in 8.3.3
(DVI/HDMI Device Discrimintion) Any device with an E-EDID that does not contain a CEA Extension or does not contain an HDMI VSDB of any valid length shall be treated by the Source as a DVI device (see Appendix C).
In 8.4.4 (Audio and Video Details) You can read:
Sink audio characteristics and support are indicated in a series of Short Audio Descriptors located in the CEA Extension’s Data Block collection. This data includes a list of audio encodings supported by the Sink and parameters associated with each of those encodings, such as number of channels supported for that format.
I have seen audio will transmitted in the blank cycles. The question is do we need the whole E-EDID stuff or not, or can work only with data island guards? I would say hardcoded 2 channels with 12-bit, lpcm is enough. The hdl-util/hdmi works with this data structures? How old gfx cards done audio? Do you have more infos?