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    emard
    @emard
    localparam real re_somethng = 3.14;
    localparam integer int_something = re_something;
    wire [31:0] wire_something = int_something;
    splinedrive
    @splinedrive
    @lawrie @emard Thanks. I have tried this and verilator is warning free:
    localparam [WAITSTATES_BIT_WIDTH-1:0] CYCLES_PER_SYMBOL = (WAITSTATES_BIT_WIDTH)'($rtoi(SYSTEM_CYCLES/BAUDRATE));
    
    ~/my_verilog/my_uart $ verilator -Wall --lint-only --top-module my_tx_uart my_tx_uart.v
    ~/my_verilog/my_uart $
    splinedrive
    @splinedrive

    @lawrie @emard The problem of my solution is. It is SystemVerilog :(. @emard yours is portable but produces the same warnings. @lawrie your solution produces the same warnings. I have downloaded ieee standard and found nothing. When I do

     verilator --language 1364-2005 -Wall --lint-only --top-module my_rx_uart my_rx_uart.v

    I get with []'() an error, because verilog 2005 doesn't support this syntax. verilator operates default with SystemVerilog. And when I remove []`(), verilog 2005 will produces the same warning again:

    %Warning-WIDTH: my_tx_uart.v:19: Operator VAR 'CYCLES_PER_SYMBOL' expects 25 bits on the Initial value, but Initial value's VARREF 'x' generates 32 bits.
                                   : ... In instance my_tx_uart

    Any idea? If not I will switch to SystemVerilog :)

    Lawrie Griffiths
    @lawrie
    The syntax seems to be supported by yosys without having to specify SystemVerilog. What you do probably depends on which tools you want to use.
    splinedrive
    @splinedrive
    :)
    splinedrive
    @splinedrive
    It is crazy the uart works with long cables with 2MBaud :). Why everbody is using 9600 Baud? I have done loopback without FIFO :)
    always @(posedge clk) begin
        if (tx_ready) begin
            transfer <= rx_valid;
            tx_data <= rx_data;
        end
    end
    emard
    @emard
    UART works up to 3Mbaud (3000000 bps). Expect few errors, any simple block retry and crc will make it error-free.
    splinedrive
    @splinedrive
    @emard Yesterday night I tried 3MBaud with 50MHz internal clock. Without any error correction. I generated 318M random data from /dev/urandom. And made a loopback without any correction and I got no errors - I check it with md5sum. I was surprised :)
    cat data.bin > /dev/ttyUSB0
    cat /dev/ttyUSB0 > data_loopback.bin
    $ du -hs data*
    318M    data.bin
    318M    data_loopback.bin
    
     $ stty -F /dev/ttyUSB2
    speed 3000000 baud; line = 0;
    min = 1; time = 0;
    -brkint -icrnl -imaxbel
    -opost
    -isig -icanon -echo
    $ md5sum data_loopback.bin data.bin
    7ff679bc7934c886a7545af78b56ea28  data_loopback.bin
    7ff679bc7934c886a7545af78b56ea28  data.bin
     $
    emard
    @emard
    Lucky you, there is some project with hdl4fpga that uploads picture to framebuffer and it requires block&crc. It could be that loopback to itself runs 100% OK but if it needs to take data at independenty clocked receiver, we experience some error every 20-100KB
    e2kgh
    @e2kgh
    Exactly, you are running on the same clock, so actually you could skip all the features, an real UART has ;-)
    splinedrive
    @splinedrive

    What Do you mean with same clock? I have

    PC<->usb<->uart<->fpga
    always @(posedge clk) begin
        if (tx_ready) begin
            transfer <= rx_valid;
            tx_data <= rx_data;
        end
    end

    I use Prolific Technology, Inc. PL2303 Serial Port to communicate with the FPGA.

    e2kgh
    @e2kgh
    Sorry, I misread. I was assuming "loopback" means on board :(
    splinedrive
    @splinedrive
    :)
    splinedrive
    @splinedrive
    @emard @e2kgh I put my fun project into https://github.com/splinedrive/my_uart for a blackicemx!
    Lawrie Griffiths
    @lawrie
    @splinedrive This is my PIO uart program that runs on the Blackice MX and the Ulx3s :)
    .program uart_tx
    .side_set 1 opt
        pull block    side 1
        set x 7       side 0 [7]
    again:
        out pins 1
        jmp x-- again        [6]
    splinedrive
    @splinedrive
    @lawrie I have seen your project I pull it :). Your are the craziest hard worker ever. I learned much from you :)
    ~/hacking/ulx3s/fpga_pio $ git pull
    remote: Enumerating objects: 55, done.
    remote: Counting objects: 100% (55/55), done.
    remote: Compressing objects: 100% (26/26), done.
    remote: Total 109 (delta 36), reused 44 (delta 27), pack-reused 54
    Receiving objects: 100% (109/109), 29.51 KiB | 332.00 KiB/s, done.
    Resolving deltas: 100% (64/64), completed with 11 local objects.
    From github.com:lawrie/fpga_pio
       fcd4f20..6648b49  main       -> origin/main
    Updating fcd4f20..6648b49
    Fast-forward
     README.md                   | 104 ++++++++-
     asm/copybit.asm             |   4 +
     asm/pwm.asm                 |   1 -
     blackicemx/Makefile         |   2 +-
     blackicemx/pio.pcf          |   2 +
     sim/copybit.mem             |   2 +
     sim/copybit.v               | 129 ++++++++++
    Lawrie Griffiths
    @lawrie
    The PIO stuff is strange, but interesting. I wonder if any other microcontrollers will copy it.
    My attempt to implement it is far from complete.
    splinedrive
    @splinedrive
    I have seen something similiar in my job on a TI-VoIP-SOC.
    emard
    @emard
    I'm trying to make PLL to sync DDS with phase accumulator to 1PPS signal from GPS or similar for long term stability. I have tried https://github.com/MorrisMA/1PPS-DPLL but it doesn't work on ECP5. Anyone to recommend something not too big and that works
    emard
    @emard
    PLL here is custom LUT-generated, not real analog PLL
    emard
    @emard
    https://johnwickerson.github.io/papers/verismith_fpga20.pdf this is interesting paper about a tool that tests yosys, vivado and quartus against correct verilog and makes them expose bugs. According to their tests quartus is best performer
    gojimmypi
    @gojimmypi
    sorry I was away from gitter! I see I missed some @'s a some time ago.
    Ben Scherrey
    @scherrey
    Cool case/keyboard/screen to hold & operate your custom designs. Hoping the guy gets funded so I can get mine. https://www.kickstarter.com/projects/jlafleur/ready-model-100-portable-computer-kit?ref=d8pkdb
    splinedrive
    @splinedrive
    Hi, I have done a hdmi reimplementation for ulx3s and blackicemx (ice40) they have the same code base. I hope you like it. I learned from other projects to take the semantic (ulx3s-examples-dvi, fpga4fun, ...) . ulx3s has DDR and SRD support and blackicemx can only DDR. I used the pmod from Luke Wren. It works only with passive resistors and works with long hdmi cables without any problems. https://github.com/splinedrive/my_hdmi_device
    emard
    @emard
    @splinedrive woow, nice work! When you are "hot" after reading standard, is there some chance to add audio over hdmi using data "islands". Here is also some fresh project for this https://github.com/hdl-util/hdmi
    splinedrive
    @splinedrive

    @emard Good point! I have read something about audio in HDMI standard https://ez.analog.com/cfs-file/__key/telligent-evolution-components-attachments/00-317-00-00-00-05-21-37/HDMISpecification13a.pdf . The point is we have a dvi implementation and hdmi needs E-EDDID Data Structure. You can read in 8.3.3

    (DVI/HDMI Device Discrimintion) Any device with an E-EDID that does not contain a CEA Extension or does not contain an HDMI
    VSDB of any valid length shall be treated by the Source as a DVI device (see Appendix C).

    In 8.4.4 (Audio and Video Details) You can read:

    Sink audio characteristics and support are indicated in a series of Short Audio Descriptors located
    in the CEA Extension’s Data Block collection. This data includes a list of audio encodings
    supported by the Sink and parameters associated with each of those encodings, such as number
    of channels supported for that format.

    I have seen audio will transmitted in the blank cycles. The question is do we need the whole E-EDID stuff or not, or can work only with data island guards? I would say hardcoded 2 channels with 12-bit, lpcm is enough. The hdl-util/hdmi works with this data structures? How old gfx cards done audio? Do you have more infos?

    splinedrive
    @splinedrive
    I mean hdl-util works with these data-structures, I can't edit my text :(
    splinedrive
    @splinedrive
    http://www.latticesemi.com/~/media/51A75F0F6DDD4F74BE69738FC8B62F24.ashx
    Unlike the DVI link which only needs one DE signal to delineate the boundary between the Video Period and the
    Control Period, the HDMI link requires at least two indicators to delineate the boundaries between the Video Data
    Period, the Data Island Period and the Control Period.
    This design has defined two indicators, Video Data Enable (VDE) and Audio/auxiliary Data Enable (ADE). The
    VDE is compatible with Data Enable (DE) used for the DVI link. When VDE is high, the HDMI link operates in the
    Video Period; when ADE is high, the HDMI link operates in the Data Island Period; when both VDE and ADE are
    low, the HDMI link operates in the Control Period. The relationship between the VDE/ADE indicators and the HDMI
    operation periods is shown in Figure 5.
    splinedrive
    @splinedrive
    @emard HDMI supports one bit audio samples it is perfect for sigma-delta-modulation.
    splinedrive
    @splinedrive

    @emard first step:

    module terc4_coding(
      input D3,
      input D2,
      input D1,
      input D0,
      output [9:0] q_out
    );
    
    always @(*) begin
      case ({D3, D2, D1, D0})
        4'b0000: q_out[9:0] = 10'b1010_011100;
        4'b0001: q_out[9:0] = 10'b1001_100011;
        4'b0010: q_out[9:0] = 10'b1011_100100;
        4'b0011: q_out[9:0] = 10'b1011_100010;
        4'b0100: q_out[9:0] = 10'b0101_110001;
        4'b0101: q_out[9:0] = 10'b0100_011110;
        4'b0110: q_out[9:0] = 10'b0110_001110;
        4'b0111: q_out[9:0] = 10'b0100_111100;
        4'b1000: q_out[9:0] = 10'b1011_001100;
        4'b1001: q_out[9:0] = 10'b0100_111001;
        4'b1010: q_out[9:0] = 10'b0110_011100;
        4'b1011: q_out[9:0] = 10'b1011_000110;
        4'b1100: q_out[9:0] = 10'b1010_001110;
        4'b1101: q_out[9:0] = 10'b1001_110001;
        4'b1110: q_out[9:0] = 10'b0101_100011;
        4'b1111: q_out[9:0] = 10'b1011_000011;
      endcase
    end
    endmodule

    :)

    emard
    @emard
    Woow great thingy! 1-bit audio is just fine for us. EDID is possible, there is i2c hardware voltage shifter that read and write EDID but I don't think it is needed if we stick to some standard that most monitors should accept. I have long time ago tried some core that works only on altera and generates sound at HDMI monitor. It doesn't read EDID, just sends islands and monitor plays them
    splinedrive
    @splinedrive
    @emard I read after work a little bit hdmi standard and the hdl-util/hdmi. I will try to extend the code with audio. I hope my display can play audio. The good thing I have this hdl-util code. Maybe it is enough only to generate some packets for audio and type whatever. We will see what comes out. But I wanted to extend my framebuffer and to write hyperram controller that was my next projects :)
    emard
    @emard
    A strange effect appears on one of my display that is DVI-only and when audio islands are inserted picture is shrinked and audio islands become visible as some video noise at border. Samsung TV shows video and plays audio normally. If you can hack something quicky, I vote for minimal core maybe 1-bit that just beeps something.
    I guess hyperram controller is more useful project than audio over video :)
    splinedrive
    @splinedrive
    @emard Who knows who designed the decoder in the tv ;) Will we see, I will work on it but I have much work also on my daily job too :)
    But Lockdown in germany makes it possible :)
    emard
    @emard
    Just follow your intuition what you think to do, that should be done first. I also want to try some hacks I never had time for, while the Great Lock still holds :)
    splinedrive
    @splinedrive
    In the moment I extend the tmds encoder with terc4 and the guards. You have determine in the tmds encoder video and audio also you have to generate these guard bands. But I have good sources the standard and the work of hdl-util. But I I want really extend the current hdmi code only with 1 bit audio bitstream for 2 channels and not the crazy things they are written in the standard.
    emard
    @emard
    I always like the reductions of the complex standard to something minimal that works everywhere (almost :)
    splinedrive
    @splinedrive
    :) The people they write these standards have the solution to sell you :)
    emard
    @emard
    First create something simple that works, then hide it in the forest of complexity that will never get used, make 3-4 books about it and make sure it's difficult to understand but easy to pay :)
    splinedrive
    @splinedrive
    I agree!
    It is possible to speedup programming on ulx3s. I have tried fujprog with 3MBaud but I wanted it faster :0
    emard
    @emard
    https://github.com/emard/esp32ecp5 can program over wifi in few seconds, much faster than ft231x JTAG over USB. Supports ftp protocol, pc initiated upload, esp32 initiated, SD card, micropython scripting ...
    splinedrive
    @splinedrive
    ok..but the transfer to esp32 takes time. I tried one time it was too slow for me
    Or something with my network?
    emard
    @emard
    ftp can directly program from net to FPGA, no need to storage bit to esp32 and program in 2nd step