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    emard
    @emard
    RAM had to be 32MB for cost about 3$. There's pin compatible 64MB but for around 12$
    sylefeb
    @sylefeb
    @lawrie agreed on spi-flash ; I have a bit banging version to boot my risc-v cores (https://github.com/sylefeb/Silice/blob/wip/projects/fire-v/smoke/mylibc/spiflash.c) and it is very convenient indeed. Doing a hardware version is on my TODO list! (also would like to investigate QSPI ...). Was not aware of @emard loader - sounds great - any recommended doc/example?
    Radu Stoichita
    @radu_stoichita_gitlab
    @emard sure thanks for the tip
    splinedrive
    @splinedrive
    You can buy hyperram pmod https://1bitsquared.com/products/pmod-hyperram to extend your memory.
    Lawrie Griffiths
    @lawrie
    @sylefeb I am not sure that between us, @emard and I, have documented the OSD and rom loader very well. There are lots of versions of the code in different projects. This is the spi slave from my Z80 template project - https://github.com/lawrie/ulx3s_z80_template/blob/main/src/osd/spirw_slave_v.v
    The rest of the code is in that osd directory.
    This is a version of the micropython code that reads and writes memory and controls the cpu remotely from the esp32 - https://github.com/lawrie/ulx3s_z80_template/blob/main/esp32/spiram.py
    The rest of the esp32 code including osd.py is in that directory.
    Here is a youtube video that shows the osd and loader being used - https://www.youtube.com/watch?v=YE7pSuZiN9Y&t=8s
    The latest version of the osd look a bit nicer.
    Lawrie Griffiths
    @lawrie
    This is my TRS 80 Model 1 implementation that has a short description on using the OSD - https://github.com/lawrie/ulx3s_z80_trs80
    Perhaps @emard knows of a better description of all this.
    Lawrie Griffiths
    @lawrie
    The OSD and loader is used by many Ulx3s projects including the Apple II, C64, ZX Spectrum, Mac Plus, QL, TI-99/4A, Amiga (OSD only), Vic 20, NES, SNES, Sega Master System, Orao, etc.
    This is a good video by @Speccery that shows the OSD used on the TI-99/4A - https://www.youtube.com/watch?v=zdST3wz00KU
    I don't think there is a Risc-V implementation on the Ulx3s that uses the OSD yet.
    sylefeb
    @sylefeb
    @lawrie thanks for the links!
    sylefeb
    @sylefeb
    (uart_echo is fixed in 'wip' branch)
    Lawrie Griffiths
    @lawrie
    @sylefeb Yes, uart_echo now works for me
    emard
    @emard
    @sylefeb @lawrie OSD loader behaves similar as SPI RAM using 32-bit byte address. FPGA behaves as SPI slave, ESP32 as SPI master. If slave needs to initiate transfer, there is additional IRQ line. Resources at SPI address space are memory mapped, RAM to upload for CPU, reset/halt control, buttons, OSD video chars, floppy disks etc. All is very simple and protocol is not too much standardized so it can be adapted to completely unusual usage. Generally for apple2 c64 vic20 mac trs80 etc we just copy-paste the same thing
    Radu Stoichita
    @radu_stoichita_gitlab
    Is it possible to run Zephyr on SaxonSoc instead of LiteX?
    Lawrie Griffiths
    @lawrie
    Yes, I used to run Zephyr on SaxonSoc on a Blackice Mx ice40 board.
    But that is on an old version of SaxonSoc, and I have never run it on a Ulx3s board. It shouldn't be too hard to get working.
    Radu Stoichita
    @radu_stoichita_gitlab
    @lawrie thanks so much i will check this for sure. I am not really getting used to Migen on Python, the documentation is very light and it seems not maintained anymore
    Lawrie Griffiths
    @lawrie
    @radu_stoichita_gitlab I do not use migen, but I have played with nmigen a bit. But I thought LiteX was still actively maintained and documented. But I think there is an issue about whether it needs to be migrated to nmigen. SpinalHDL is well documented and SaxonSoc Linux is pretty well documented, but other uses of SaxonSoc are not currently well supported or documented.
    Radu Stoichita
    @radu_stoichita_gitlab
    @lawrie very insteresting thoughts. I am a software developer in my daily life and it is true that SpinalHDL documentation is much easier for me to understand. What kind of features are you missing information for in SaxonSoc? Is there any better alternative?
    Lawrie Griffiths
    @lawrie
    The issue with SaxonSoc is that it is fast-moving technology and very few people are working on it. Zephyr was implemented on an early version of it, but more recently all the emphasis has been on Linux.
    VexRiscv is in most people's opinion the best 32-bit open source Risc-V implementation because of its speed, size and configurability. It is about the only one that supports Linux. It is written in SpinalHDL. If you are using a SoC, there are a few choices such as the older SpinalHDL ones like Murax and Briey, or LiteX. But I believe that SaxonSoc is the best one.
    Lawrie Griffiths
    @lawrie
    There are lots of other choices for Risc-V like picorv32, ultraembedded/riscv, the Silice Risc-V implementations, and minerva and lambda-soc in nmigen.
    But I believe VexRiscv and SaxonSoc is the best. It just needs more people working on it, particularly the non-Linux versions.
    Lawrie Griffiths
    @lawrie
    VexRiscV LiteX Linux probably has a wider user base than SaxonSoc and runs on a lot more boards. It has more support for peripherals, but SaxonSoc's support is growing and we are likely to see an FPU and USB host support sometime soon.
    e2kgh
    @e2kgh
    They both (SaxonSOC and LiteX) scare me every time I look at their web pages. Install instructions are for ubuntu 14, which is pretty old.
    Radu Stoichita
    @radu_stoichita_gitlab
    I have a little side project for which I need flexible firmware. Basically i went with SaxonSoc because I had many many questions with LiteX that i didn't find answers to. Like you said they evolve quite fast and honestly I have soend tens of hours only following the instructions and building the systems with not much understanding about the inner works of it. Basically, Linux is overkill for the application I try to build. I have successfully booted standalone firmware on Saxon after many many hours but when I consider going further into the understanding of these platforms, the learning curve is very tough for me. I only I had an ARM core with onboard FPGA and RAM controller for 3$ that would be great but there is no such device. Initially I soent some time evaluating Latticemico32 with diamond builder however they don't have native support for SDR only DDR
    @e2kgh right it's scary you need to follow very closely and not deviate. However I run everything on KDE 20.04 and didn't have much issues so far
    emard
    @emard
    We have onboard ESP32 and it can run micropython or plain C as microcontroller, access SD card wifi, bluetooth - maybe it can help somehow for your application
    Radu Stoichita
    @radu_stoichita_gitlab
    @emard exactly how I intend to use it for network connectivity, this is an awesome combo on this board! Just wondering what would be the speed for transferring 100MiB between FGBA and ESP32
    I need the memory ESP32 has not and on the other hand I need the speed for digital ADC application basically 😊
    emard
    @emard
    ESP32 is not very fast, it's about 100-200 KB/s (kilobytes per second) at wifi side. ESP32-FPGA can use SPI, probably slightly faster than wifi. OK currently ESP32 has not much memory. We plan new board design that will have ESP32-WROVER, it will have 2MB PSRAM internally, not big but more than now
    There is also f32c project, slightly unmaintained, this one is reduced MIPS core 100 MHz, SDRAM support, arduino/gcc programmable, very efficient but diamond-only (no ghdl/yosys)
    Radu Stoichita
    @radu_stoichita_gitlab
    @emard cool I will have a look at f32c thank you
    emard
    @emard
    It is in portable multivendor vhdl, compared to saxonsoc or nmigen it's relatively dirty soc'd but has gcc and arduino support. Not very fine support like esp32, but something is working. ulx3s selftest is done with f32c
    Radu Stoichita
    @radu_stoichita_gitlab
    👍👍👍
    Radu Stoichita
    @radu_stoichita_gitlab
    Nice Gadget but beware of potentially lethal voltage on the raw tube end and PSU. You could contact this guy?
    splinedrive
    @splinedrive
    I will order it I want to generate this old school analog signals!
    VGA signal generator takes 4 lines verilog but with this paper it becomes rocket scienes https://bit.ly/3r3LubY
    e2kgh
    @e2kgh
    @emard : so, are you planning on any updates to the F32C, ever? ;-)
    It was a nice piece & environment ...
    About tool chains ... So, how do you guys set up your system? There is the repository from KOST, there is LiteX, SaxonSOC, and they like specific versions of Java, GHDL, Verilator, etc. It is (at least for me) hard to understand, that if something went wrong, it was a problem with the tool chain, or mine, or somewhere in the PATH, I'm getting the wrong utility pulled in? Any writeups, how to set up a "clean" system, not having three/four versions of the same tools?