Or optionally this - http://www.cpctech.org.uk/docs/extdsk.html
@rob-ng15 @lawrie how are things on the PS/2 keyboard + Silice front? (I lost track these past few days due to other workloads)
Hi @lawrie @sylefeb I have a PS/2 keyboard that works with the ULX3s :) It is a KB2106C that I got from https://www.cclonline.com/product/76320/KB-2106C/Keyboards/CiT-KB-2106C-USB/PS2-Combo-Keyboard/KBD0426/
Gives keycodes from the Silice using the PS/2 that @lawrie wrote, and works with the Jupiter Ace emulator. Very happy!
@lawrie yes, floppy is the cool medium, only I see they complicate the format why so much science aiiieeee. For the tapes, how about to support single image loading, like c64/vic20 and similar. If we assume it's similar, then if we find what memory locations change after tape loading then we just patch ROM for this to happen and I suppose it's the minimal effort to get something. Of course only single part will load, multipart tapes won't work this way
I think they are in some xml file, I have scripts in ulx3s-misc and makefiles for most projects tp compile same example source with both yosys and diamond eg. https://github.com/emard/ulx3s-misc/tree/master/examples/dvi
hey @emard, any interest in verilator for some of the ulx3s cores?
I'm using verilator with sdl/imgui/opengl to do simulations with video output for a simple mister core I'm building, and wanted to do it for c64, but half that core is vhdl so it wouldn't work without some vhdl2vl, which made me think of ulx3s
@sajattack:matrix.org Great if you know verilator, I never used it (maybe lazy me). I have USB core and some keyboards don't work, they enumerate but keypress sends no USB report. There's a bug which I can't find. I would probably need real wire USB analyzer, but if you think verilator could help, that's cool to simulate. I think I have verilog-only version. Some is vhdl but its convertible to verilog with vhd2vl
this is my little video sim https://github.com/sajattack/Gigatron_MiSTer/blob/master/verilator/sim_main.cpp
The problem is with the keyboard might be the interrupts, which are not frequent enough. They are currently one per frame but should be about 6 per frame. The algorithm for generating and clearing the interrupt is strange and I have not attempted it. The Mist/Mister uses an algorithm that was derived by reverse engineering the Amstrad gate array chip, but is produces strange verilog that uses lots of clocks. I will probably try something simpler. The clock speed and audio also needs work on it. I have been doing other things for the last week or so.
latest nightly build trellis has problem with 12F but I have 85F too :)
noob question - I am seeing strange failures in my design at higher clock rates. in my yosys/pnr output, the first clk max frequency is a fail, but the second is a pass. is this okay? or is a failure at the first time (prior to the slack histogram) still a real failure
@emard I have changed the Amstrad CPC pll to use a 16Mhz cpu clock, so I can divide it and run the Z80 at the correct 4MHz clock rate. However the real Amstrad CPC's gate array introduces some wait states, and I am not emulating that, so my version runs a bit fast, equivalent to setting the fast option in the Mister version. I am still using 25MHz and 125MHz VGA and HDMI clocks. All this makes it harder to support an SDRAM option.
sxpert @sxpert is installing the tools on his brand new macbook
31.51. Executing JSON backend.
ERROR: Module $paramod$17f8df79e41cf412d10145c627e098e0ef3768b8\TRELLIS_FF contains processes, which are not supported by JSON backend.
@sxpert HI, glad to see you continue saturn cpu, is there something I can pull and try to compile
@sthornington You can use ecp5pll.sv but around reported error line, there is comment about part of the source that should be put in the comment for diamond to swallow it. I just can't match same systemverilog source to pass both yosys and diamond