Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
    emard
    @emard
    @sajattack:matrix.org Great if you know verilator, I never used it (maybe lazy me). I have USB core and some keyboards don't work, they enumerate but keypress sends no USB report. There's a bug which I can't find. I would probably need real wire USB analyzer, but if you think verilator could help, that's cool to simulate. I think I have verilog-only version. Some is vhdl but its convertible to verilog with vhd2vl
    sajattack
    @sajattack:matrix.org
    [m]
    yeah I'm not sure if verilator is cut out for that one
    emard
    @emard
    for demo/example it is great if we had makefile for some other core for verilator, like dvi demo, hex decoder, spi display driver and similar
    sajattack
    @sajattack:matrix.org
    [m]
    emard
    @emard
    oho, I should take a look at this, I downloaded it but first I have to do some research about depedencies and installing them
    sajattack
    @sajattack:matrix.org
    [m]
    screenshot for added enticement
    sameerCoder
    @sameerCoder
    HI,
    is this group for pyroms ocean model?
    EnJens
    @EnJens
    emard
    @emard
    @lawrie I compiled amstrad for 12F, it booted out of the box! A small issue is that it looses keystrokes or I have to hold key very long in order to reliably accept it. Now I don't remember was original machine so lowsy (could be :)
    emard
    @emard
    OK - i just saw git log "partialy working keyboard" this explains
    Lawrie Griffiths
    @lawrie
    The problem is with the keyboard might be the interrupts, which are not frequent enough. They are currently one per frame but should be about 6 per frame. The algorithm for generating and clearing the interrupt is strange and I have not attempted it. The Mist/Mister uses an algorithm that was derived by reverse engineering the Amstrad gate array chip, but is produces strange verilog that uses lots of clocks. I will probably try something simpler. The clock speed and audio also needs work on it. I have been doing other things for the last week or so.
    Lawrie Griffiths
    @lawrie
    @emard I have pushed the changes to the interrupt handling and it seems to have the keyboard
    emard
    @emard
    HI! Thanx! Let me check it!
    emard
    @emard
    Info: Running main analytical placer.
    ERROR: Failed to expand region (0, 0) |_> (72, 50) of 12188 TRELLIS_SLICEs
    0 warnings, 1 error
    latest nightly build trellis has problem with 12F but I have 85F too :)
    emard
    @emard
    on 85F it builds but scroll doesn't work properly, instead of scroll text wraparounds from top but not on first column, strange :)
    Lawrie Griffiths
    @lawrie
    I have only run it on the 85F. I noticed it was close to the BRAM limit on the 12F. Yes, that scrolling issue is strange. I don't have any ideas on what could cause that.
    Lawrie Griffiths
    @lawrie
    @emard The scrolling problem is because I did not realise that the CPC used hardware scrolling with the CRTC, so I need to implements some of the CRTC registers.
    Lawrie Griffiths
    @lawrie
    @emard I have pushed a change that seems to fix the scrolling problem.
    emard
    @emard
    HI ok I will pull but am away from home, have board only, no monitor. from next week I can try cpc646 scroll on real monitor
    splinedrive
    @splinedrive
    Hi, could some one explain me or have code to use SB_PLL40_2F_CORE. I want to use 2 PLLs in ice40, but I found no examples. And why icepll will not generates the config for 2 clocks. If I get knowledge I would like to extend icepll with it.
    Simon Thornington
    @sthornington
    noob question - I am seeing strange failures in my design at higher clock rates. in my yosys/pnr output, the first clk max frequency is a fail, but the second is a pass. is this okay? or is a failure at the first time (prior to the slack histogram) still a real failure
    Lawrie Griffiths
    @lawrie
    I don't think it is a problem: nextpnr has just tried harder and made it achieve the clock rate. ( At least that is my interpretation). As nextpnr is rather pessimistic about FMax, a lot of designs that fail in the second pass still work.
    Simon Thornington
    @sthornington
    Ok. I think my problem is elsewhere then
    Lawrie Griffiths
    @lawrie
    @emard I have changed the Amstrad CPC pll to use a 16Mhz cpu clock, so I can divide it and run the Z80 at the correct 4MHz clock rate. However the real Amstrad CPC's gate array introduces some wait states, and I am not emulating that, so my version runs a bit fast, equivalent to setting the fast option in the Mister version. I am still using 25MHz and 125MHz VGA and HDMI clocks. All this makes it harder to support an SDRAM option.
    sxpert @sxpert is installing the tools on his brand new macbook
    sxpert
    @sxpert
    my CPU is getting a nice workout
    Simon Thornington
    @sthornington
    is it still the case that to try a build of the examples with the latest diamond toolchain (3.12) I must not use ecp5pll.sv ?
    sxpert
    @sxpert
    can't seem to get it to build with gui though
    sxpert
    @sxpert
    gah, nuked all my brew stuff with a messed up makefile ;(
    sxpert
    @sxpert
    there, fixed, that took a while
    emard
    @emard
    @lawrie I currently can't compile cpc464, tried 12F and 85F and got same error
    31.51. Executing JSON backend.
    ERROR: Module $paramod$17f8df79e41cf412d10145c627e098e0ef3768b8\TRELLIS_FF contains processes, which are not supported by JSON backend.
    @sxpert HI, glad to see you continue saturn cpu, is there something I can pull and try to compile
    @sthornington You can use ecp5pll.sv but around reported error line, there is comment about part of the source that should be put in the comment for diamond to swallow it. I just can't match same systemverilog source to pass both yosys and diamond
    it's around line 184
      // diamond: won't compile this, comment it out. Workaround follows using division by zero
    
      if(error_out0_hz) $error("out0_hz tolerance exceeds out0_tol_hz");
      if(error_out1_hz) $error("out1_hz tolerance exceeds out1_tol_hz");
      if(error_out2_hz) $error("out2_hz tolerance exceeds out2_tol_hz");
      if(error_out3_hz) $error("out3_hz tolerance exceeds out3_tol_hz");
    
      // diamond: trigger error with division by zero, doesn't accept $error()
      localparam trig_out0_hz = error_out0_hz ? 1/0 : 0;
      localparam trig_out1_hz = error_out1_hz ? 1/0 : 0;
      localparam trig_out2_hz = error_out2_hz ? 1/0 : 0;
      localparam trig_out3_hz = error_out3_hz ? 1/0 : 0;
    emard
    @emard
    @lawrie wait something is wrong completely with yosys/nextpnr binaries nothing compiles, not only your cpc
    emard
    @emard
    I compiled it, last binary that works for me is yesterday's fpga-toolchain-linux_x86_64-nightly-20210315.tar.xz and scroll now works perfectly, who would expect scroll acceleration hardware on this machine!
    Lawrie Griffiths
    @lawrie
    @emard I still need to get the sound working correctly before looking at loading software. I am using the jotego jt49 version of the sound chip, but currently if I get the timing right, the sound is an octave high. I am also discarding a lot of the sound resolution. I need to use your pwm audio code.
    Dobrica Pavlinušić
    @dpavlin
    @emard @lawrie I had same problem with yosys yesterday trying saxonsoc and there seems to be issue reported about it YosysHQ/yosys#2667 - I'm not sure how to apply blackbox
    Lawrie Griffiths
    @lawrie
    @dpavlin @Dolu1990 and I have just tried the latest dev-0.3 version of SaxonSoc on the Ulx3s ans it works, including LAN8720 networking - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp
    I did not understand the blackbox stuff either, but presumably this problem will be fixed in a new version of the nightly tools.
    David Shah
    @daveshah1
    It should be fixed already
    Simon Thornington
    @sthornington
    I had a problem using yosys fpga-toolchain nightly with my project, complained about a combinational loop. Will try avain with latest tonight.
    sylefeb
    @sylefeb
    Hi everyone, I'd like to improve my sdcard reader ; right now it requires 48 cycles to read one byte at 50 MHz (SPI on SDHC). Works but slow. I was wondering how fast everyone is able to read data from the sdcard? (FPGA side) I read about a 'fast spi' cmd6 - anyone has experience with that?
    emard
    @emard
    @sylefeb technically top speed at ULX3S should be about 14 MByte/s with 4-bit transmission and limited with electical interface (3.3V supply, no switching to 1.8V). I have not tried fast mode but https://opencores.org/projects/sdcard_mass_storage_controller has some project for that
    sylefeb
    @sylefeb
    Thanks @emard !