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    emard
    @emard
    HI ok I will pull but am away from home, have board only, no monitor. from next week I can try cpc646 scroll on real monitor
    splinedrive
    @splinedrive
    Hi, could some one explain me or have code to use SB_PLL40_2F_CORE. I want to use 2 PLLs in ice40, but I found no examples. And why icepll will not generates the config for 2 clocks. If I get knowledge I would like to extend icepll with it.
    Simon Thornington
    @sthornington
    noob question - I am seeing strange failures in my design at higher clock rates. in my yosys/pnr output, the first clk max frequency is a fail, but the second is a pass. is this okay? or is a failure at the first time (prior to the slack histogram) still a real failure
    Lawrie Griffiths
    @lawrie
    I don't think it is a problem: nextpnr has just tried harder and made it achieve the clock rate. ( At least that is my interpretation). As nextpnr is rather pessimistic about FMax, a lot of designs that fail in the second pass still work.
    Simon Thornington
    @sthornington
    Ok. I think my problem is elsewhere then
    Lawrie Griffiths
    @lawrie
    @emard I have changed the Amstrad CPC pll to use a 16Mhz cpu clock, so I can divide it and run the Z80 at the correct 4MHz clock rate. However the real Amstrad CPC's gate array introduces some wait states, and I am not emulating that, so my version runs a bit fast, equivalent to setting the fast option in the Mister version. I am still using 25MHz and 125MHz VGA and HDMI clocks. All this makes it harder to support an SDRAM option.
    sxpert @sxpert is installing the tools on his brand new macbook
    sxpert
    @sxpert
    my CPU is getting a nice workout
    Simon Thornington
    @sthornington
    is it still the case that to try a build of the examples with the latest diamond toolchain (3.12) I must not use ecp5pll.sv ?
    sxpert
    @sxpert
    can't seem to get it to build with gui though
    sxpert
    @sxpert
    gah, nuked all my brew stuff with a messed up makefile ;(
    sxpert
    @sxpert
    there, fixed, that took a while
    emard
    @emard
    @lawrie I currently can't compile cpc464, tried 12F and 85F and got same error
    31.51. Executing JSON backend.
    ERROR: Module $paramod$17f8df79e41cf412d10145c627e098e0ef3768b8\TRELLIS_FF contains processes, which are not supported by JSON backend.
    @sxpert HI, glad to see you continue saturn cpu, is there something I can pull and try to compile
    @sthornington You can use ecp5pll.sv but around reported error line, there is comment about part of the source that should be put in the comment for diamond to swallow it. I just can't match same systemverilog source to pass both yosys and diamond
    it's around line 184
      // diamond: won't compile this, comment it out. Workaround follows using division by zero
    
      if(error_out0_hz) $error("out0_hz tolerance exceeds out0_tol_hz");
      if(error_out1_hz) $error("out1_hz tolerance exceeds out1_tol_hz");
      if(error_out2_hz) $error("out2_hz tolerance exceeds out2_tol_hz");
      if(error_out3_hz) $error("out3_hz tolerance exceeds out3_tol_hz");
    
      // diamond: trigger error with division by zero, doesn't accept $error()
      localparam trig_out0_hz = error_out0_hz ? 1/0 : 0;
      localparam trig_out1_hz = error_out1_hz ? 1/0 : 0;
      localparam trig_out2_hz = error_out2_hz ? 1/0 : 0;
      localparam trig_out3_hz = error_out3_hz ? 1/0 : 0;
    emard
    @emard
    @lawrie wait something is wrong completely with yosys/nextpnr binaries nothing compiles, not only your cpc
    emard
    @emard
    I compiled it, last binary that works for me is yesterday's fpga-toolchain-linux_x86_64-nightly-20210315.tar.xz and scroll now works perfectly, who would expect scroll acceleration hardware on this machine!
    Lawrie Griffiths
    @lawrie
    @emard I still need to get the sound working correctly before looking at loading software. I am using the jotego jt49 version of the sound chip, but currently if I get the timing right, the sound is an octave high. I am also discarding a lot of the sound resolution. I need to use your pwm audio code.
    Dobrica Pavlinušić
    @dpavlin
    @emard @lawrie I had same problem with yosys yesterday trying saxonsoc and there seems to be issue reported about it YosysHQ/yosys#2667 - I'm not sure how to apply blackbox
    Lawrie Griffiths
    @lawrie
    @dpavlin @Dolu1990 and I have just tried the latest dev-0.3 version of SaxonSoc on the Ulx3s ans it works, including LAN8720 networking - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp
    I did not understand the blackbox stuff either, but presumably this problem will be fixed in a new version of the nightly tools.
    David Shah
    @daveshah1
    It should be fixed already
    Simon Thornington
    @sthornington
    I had a problem using yosys fpga-toolchain nightly with my project, complained about a combinational loop. Will try avain with latest tonight.
    sylefeb
    @sylefeb
    Hi everyone, I'd like to improve my sdcard reader ; right now it requires 48 cycles to read one byte at 50 MHz (SPI on SDHC). Works but slow. I was wondering how fast everyone is able to read data from the sdcard? (FPGA side) I read about a 'fast spi' cmd6 - anyone has experience with that?
    emard
    @emard
    @sylefeb technically top speed at ULX3S should be about 14 MByte/s with 4-bit transmission and limited with electical interface (3.3V supply, no switching to 1.8V). I have not tried fast mode but https://opencores.org/projects/sdcard_mass_storage_controller has some project for that
    sylefeb
    @sylefeb
    Thanks @emard !
    Matt Ettus
    @MattEttus
    Can anyone suggest where to find a good wishbone to SDRAM module which works well on ulx3s?
    ildus
    @ilduso_twitter
    @MattEttus https://opencores.org/projects/sdram_16bit this one is working for me, but needs more testing, ulx3s v3.0.8, SDRAM_TARGETshould be changed
    Matt Ettus
    @MattEttus
    @ilduso_twitter thanks, I'll take a look at it
    francis2tm
    @francis2tm
    Hey! I'm a beginner. I want to try to deploy the SaxonSoc in the ulx3s 85F board. Unfortunately, the SaxonSoc like it doesn't have a lot of documentation and specially introduction to noobs like me. I've seen they have instructions here https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp , yet it seems like it's assuming you want to build linux with buildroot, but I'm looking for a standalone, no OS, implementation. Does someone have any resource to help me getting started?
    Thanks in advance!
    1 reply
    Irvise
    @irvise:matrix.org
    [m]
    If you do not want linux, that is fine, don't do the sdcard part and just create and ftp server on the esp32 and load the bitstream of the cpu and the program that you want to run on it.
    francis2tm
    @francis2tm
    @irvise:matrix.org thanks! Makes sense ;) I'll try
    Lawrie Griffiths
    @lawrie
    @francis2tm I am working with @Dolu1990 to produce a Ulx3sMinimal version in the dev-0.3 branch, which can be used as a starting point for non-Linux implementations. Several people seem to be interested in building non-Linux versions and the ones we currently have are old and deprecated.
    Radu Stoichita
    @radu_stoichita_gitlab
    Hi Lawrie, i am interested as well! Many thanks, just spent days trying to orchestrate a clean project from scratch with Spinal in order to understand the whereabouts in details.
    francis2tm
    @francis2tm
    Hey @lawrie
    Amazing, I'm looking forward to see your work
    Many thanks!
    Lawrie Griffiths
    @lawrie
    And there is currently a problem that reset is the wrong polarity.
    The minimal hardware implementation has just gpio, uart and 32Kb of BRAM.
    Radu Stoichita
    @radu_stoichita_gitlab
    Cool thanks will check it out asap 🙏
    Lawrie Griffiths
    @lawrie
    You load software into it via a hex file, which requires rebuilding the bitstream when you run the software.
    There are lots of other ways of running software. In previous versions of SaxonSoc, I had lots more examples, but SaxonSoc is changing so fast that it is hard to maintain them, so we are not likely to have many example configurations.
    Note that my Scala and SpinalHDL skills are not that good, so I need lots of help from @Dolu1990 to get this stuff working.
    Lawrie Griffiths
    @lawrie
    For those interested in the Linux versions, the latest dev-0.3 README tells you how to build a Linux system that uses an FPU - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp. It runs mandelbrot about 100 times faster than without an FPU.
    For non-Linux systems, the other ways of running software include loading binaries into flash memory and copying it to SDRAM like the Linux version does. That would need SDRAM support added to the hardware configuration.
    5 replies
    Another possible way is to run it in place from flash. That needs XIP support adding to the hardware.