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    emard
    @emard
    @rvalles:matrix.org the pmod with 2 USB's should work. If it doesn't work, you don't have keyboard that can provide PS/2 protocol. PS/2 should be provided when both D+ and D- lines are pulled up, Normal USB either pulls up D+ or D- but not both for a long time, so that's how keyboard "knows". Read at the bootom of keyboard if it supports PS/2 or in manual there's known keyboard that can currently be obtained and users reported it working. We have USB host core but it is long and heavy, already complex design like amiga will not like it, fmax reduction and long compile times...
    For amiga I had working USB core for joystick, but for kbd you would need additional one, but PS/2 protocol is much lighter and a better choice in this situation. Minimig has linux host that accepts USB kbd and probably converts to PS2 when going to core
    rvalles
    @rvalles:matrix.org
    [m]
    By minimig you mean mister there, I guess? That's my least favorite part about mister.
    The other annoyances are no support for 1MB (AROS...) rom, and Amiga serial port is wired... who knows where. I'd have to look into that too.
    Ultimately, for what I need to do, it'll likely be better to try and get AROS working on my A1200 instead, and do my work against that.
    emard
    @emard
    By minimig I also mean https://github.com/emard/Minimig_ECS for ULX3S. I'm not expert in amiga emuation field, I just ported it without understanding how ROM etc things are loaded. I know it has additional 68k core handling OSD and loading. There is more fresh activity https://github.com/rkrajnc/Minimig-AGA_MiSTer this one has some risc cpu instead of 68k to handle OSD and loading
    Irvise
    @irvise:matrix.org
    [m]
    Hello. I want to follow this blog to write a barebones Ada program on top of the SaxonSOC CPU.
    The title says arm, but startup-gen also works with RISC-V.
    In principle, I just need to declare the memory regions (rom, ram).
    Irvise
    @irvise:matrix.org
    [m]
    From what I have read of SaxonSOC (using prebuilt binaries: https://github.com/lawrie/saxonsoc-ulx3s-bin/tree/master/Smp ) once the cpu bitstream is loaded, the cpu jumps to 0x340000 which should contain fw_jump.bin and it then jumps to 0x380000 for u-boot.
    Correct me if I am wrong, but in principle, if I generate a program that load to the address 0x380000 it should "just work", isn't it? Without loading u-boot of course.
    And where can I find more info on what memory addresses are being used for MMIO? The VexRisc documentation (code) is not very clear on that.
    In the end I want to get a blinking led without having to go trough the use of Linux (barebones).
    Dolu1990
    @Dolu1990

    @irvise:matrix.org

    0x340000

    That's the flash address. the CPU copy that part of the flash to the SDRAM at 0x80F80000 (global address). See :

    Then it does similar things with uboot but with that set of addresses : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/app/bootloaderConfig.h#L22

    if I generate a program that load to the address 0x380000 it should "just work"

    Yes, as long you programe is complied to sit at 0x80F00000 in the global memory space

    And where can I find more info on what memory addresses are being used for MMIO

    This autogenerated header file contains all the peripheral addresses :

    https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/include/soc.h#L64

    blink

    See https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/blinkAndEcho/src/main.c
    used with https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/include/bsp.h#L15

    you can compile it using the command "saxon_standalone_compile blinkAndEcho" It will sit where uboot sit (see https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/bsp/radiona/ulx3s/smp/linker/default.ld#L1)

    1 reply
    Radu Stoichita
    @radu_stoichita_gitlab
    Or you can leave the bootloader as is uboot as is and change the bootcmd to load from mmc 0:1 the standalone firmware and run it
    1 reply
    This avoids resynthetize all fpga bitstream for program change
    I left bootloader. Hex and uboot
    Just use a helper to update standalone firmware to SD card
    Irvise
    @irvise:matrix.org
    [m]
    And one generic question. Can SaxonSOC be built? (https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp)
    I have been having constant errors with sbt not being able to download dependencies.
    I have been fighting and struggling to get Litex-VexRISC to build and decided to go back to SaxonSOC, but that one has the exact same dependencies issues.
    See:
            Server access error at url http://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt.ivy/ivy/2.3.0-sbt-839fad1cdc07cf6fc81364d74c323867230432ad/ivys/ivy.xml (java.net.ConnectException: Connection refused (Connection refused))
    
            Server access error at url http://repo.typesafe.com/typesafe/ivy-releases/org.scala-sbt.ivy/ivy/2.3.0-sbt-839fad1cdc07cf6fc81364d74c323867230432ad/jars/ivy.jar (java.net.ConnectException: Connection refused (Connection refused))
    Those URLs do not exist. How does one then go about building SaxonSOC? Is it a temporary network issue?
    Radu Stoichita
    @radu_stoichita_gitlab
    I have built the Ulx3sSmp on the 0.3 branch without issues
    Maybe check your connectivity or remove the sbt cache directories / reinitialize project
    Best woyld be to follow the readme for a clean clone
    Sorry I struggled myself very much for the builds
    Dolu1990
    @Dolu1990
    Yes that's likely some server down online
    Seems like there may be some solution to have backups
    I'm locking that right now
    Now worries, about the struggle, different workflow are most of the time a mess to pick up ^^
    I tried to reproduce the same issue, can't. Can you PM me the whole logs ?
    Irvise
    @irvise:matrix.org
    [m]
    I tried building the 0.3 branch too following the step by step README. To no avail due to the error above.
    And I indeed tried to force rebuilds by deleting ~/.sbt and ~/.ivy2 but the error persisted.
    I will try it again later, if the error persists, I will send you the logs @Dolu1990 .
    Irvise
    @irvise:matrix.org
    [m]
    Question: is there a way to generate a CMSIS-SVD descriptor of the VexRiscv CPU / SaxonSOC platform?
    I would suspect that it should be created (by default or behind a flag) during synthesis.
    That would greatly help me with my project (https://github.com/AdaCore/svd2ada also works with RISC-V).
    Dolu1990
    @Dolu1990

    @irvise:matrix.org

    Question: is there a way to generate a CMSIS-SVD descriptor of the VexRiscv CPU / SaxonSOC platform?

    There is nothing in place actualy. It would be cool to have, but actualy, the dev was focused on other aspects (linux, more peripherals, mooore power, ..)

    Irvise
    @irvise:matrix.org
    [m]
    So I take it that the C headers with the addresses and such, were handcrafted no?
    Rob Taylor
    @rob_chipflow:matrix.org
    [m]
    @Dolu1990: Is there a pregenerated vexriscv or murex around? I have a team that wants to use it to test some FPGA tooling
    Lawrie Griffiths
    @lawrie
    The BSP generator could probably be extended to generate a CMSIS-SVD descriptor. I have been doing some work for Rust recently and an svd file would help a lot in generating a Rust HAL for SaxonSoc.
    Lawrie Griffiths
    @lawrie
    I think Litex Vexriscv does generate an svd file - see http://pepijndevos.nl/2020/08/04/a-rust-hal-for-your-litex-fpga-soc.html
    1 reply
    Lawrie Griffiths
    @lawrie
    @rob_chipflow:matrix.org What is it that you want? Is it pregenerated Verilog or a prebuilt bitstream for a device such as the Ulx3s?
    Is it Murax that you want rather than the much newer SaxonSoc, and if so is it any particular SoC configuration?
    Lawrie Griffiths
    @lawrie
    There are some rather old VexRiscv generated verilog files here - https://github.com/m-labs/VexRiscv-verilog, but I believe those are designed to be used with a Wishbone bus and Litex peripherals.
    Rob Taylor
    @rob_chipflow:matrix.org
    [m]
    lawrie (Lawrie Griffiths): hi, it’s some generated verilog for the FABulous open fpga folk to try out on their tooling