Hi, on e-radionica.com they say
"This product is retired and we won't sell it anymore. This page is for reference only."
on the ulx3s page.
Is this an error (that the product is retired) ? Or a kind true ?
Is the ULX4M is going to replace it ?
I have one ULX3S and was planning to buy one more.
Apparently still not available at mouser ! I'll have a look at envox.
I have done new cpu single cycle rv32i https://twitter.com/splinedrive/status/1577734635307651073
Should be the base for pipelined version as next
Hi all - after a long pause I am thinking about FPGA projects again. I have not had much hobby time in the interim period, but what time I had went to working with System III Unix and the Sipeed Riscv board ( see here ). That is working now.
For that I am using the Plan 9 C compilers by Ken Thompson and Rob Pike, the Riscv backend was done by Richard Miller. It compiles both RV32 and RV64 code and the compilers are small enough (~200KB) that they can run native easily. They can be found here: https://gitlab.com/pnru/riscv-kencc
It is actually a family of compilers, that can also do x86, ARM and M68K (and several more).
I was looking at ways to run SysIII on the ULX3S as well and came across the RVSoc project, which can be found here: https://www.arch.cs.titech.ac.jp/wk/rvsoc/doku.php
It is only some 5,000 lines of plain Verilog and Linux ('buildroot') capable - but undoubtedly it will be slow, because I don't think it has a memory cache. The CPU is RV32IMAC with a 32 bit MMU.
Has anybody tried to get RVSoc running on an ULX3S board?
I was thinking about adding the cache that I did for Oberon and never got quite working. How has Yosys/NextPNR improved over the past two years in this area (large, dual port block ram usage)?? Pre-pandemic it was 'being worked on' I remember.
I noticed that Orangecrab is no longer doing nightly builds. Is YosysHQ now the preferred source for those? (I mean https://github.com/YosysHQ/oss-cad-suite-build).