- Gitter

All Rooms

4 Rooms 266 People

General

Discussions about the VHDL language, VHDL tools chains and frameworks around VHDL.
- VHDL
- FPGA
- Simulation
- Verification
- HDL
- Intel
- Altera
- Xilinx
- Lattice
- Mentor
- Mentor Graphics
- Aldec
- Synopsys
- GHDL
- GTKWave
- UVVM
- OSVVM
- VUnit
- PoC
- LibreCores
- FOSSi
- Xilinx ISE
- Xilinx Vivado
- Lattice Diamond
- Alte
152 People
Lobby

Open Source VHDL Group (OSVG)
- VHDL
- OSVG
- Verification
- Simulation
- CoreLib
- Open Source
75 People
Interfaces

Discussions about VHDL-2019 interfaces. See https://github.com/VHDL/Interfaces
20 People
meetings

Discuss meeting related things...
- OSVG
- Meeting
- VHDL
- Open Source
- Verification
- Simulation
19 People