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Richard Head
@trickyhead_gitlab
yes, concatenate
(a,b) would be 2d array or a record
(a&b) is ambiguous in the above context
DrPi
@drpi:matrix.org
[m]
Because of the indexes ?
Richard Head
@trickyhead_gitlab
because it could return a bit_vector or bd2d
1 reply
I think removing () makes it unambiguous
either way, its not that clear to the reader
DrPi
@drpi:matrix.org
[m]
Right. I forgot you have to give a dimension to bv2d.
Richard Head
@trickyhead_gitlab
if k was declared with a range, and () removed then all is solved
or constant k : bv2d := bv2d'(a&b); (if it allows the fact the ranges of a and b dont match
because for an unconstrained array, all elements must have the same range
DrPi
@drpi:matrix.org
[m]
constant k: bv2d (a'Subtype)(b'Subtype) := ...;
I think this is not what you want.
Richard Head
@trickyhead_gitlab
a'subtype is a bit_vector, not the required natural
DrPi
@drpi:matrix.org
[m]
Want you want is a one dimension array right ?

a'subtype is a bit_vector, not the required natural

You need to constrain the arrays.

Richard Head
@trickyhead_gitlab
yes
constant k : bv2d (open)(a'range) := a & b;
DrPi
@drpi:matrix.org
[m]
You have to better describe what you want to achieve at the end.
open is not an option in this case
Richard Head
@trickyhead_gitlab
why not?
constants are allowed to be declared with no range
range is infered from the initial value
DrPi
@drpi:matrix.org
[m]
Right.
It seems your mixing 2 concepts here. You really should explain what your trying to do.
Sorry, have to go now.
d3jones-metrics
@d3jones-metrics

I am trying to clarify aggregates for arrays whose element type is unconstrained.

constant k: bv2d := (a,b);

is intended to be a positional array aggregate, whose type is array(2 elements) of array(3 elements) of bit.

I am using a constant because I don't need to constrain the definition. If I used a variable then I'd have to provide constraints on bv2d which would allow the aggregate to dodge the question, as any ranges on the aggregate would be superseded once assigned to the variable.

If the aggregate has to figure itself out using its own context, then what are the bounds of each array? Is this defined in the LRM?

Richard Head
@trickyhead_gitlab
so GHDL compiles @d3jones-metrics code giving k'range = 0 to 1 and k(0)'range = 1 to 3
d3jones-metrics
@d3jones-metrics
And so does Aldec. But is this defined in the LRM, or are these vendors guessing?
Why is the second dimension not (4 downto 2)?
Or anything else for that matter?
Richard Head
@trickyhead_gitlab
constant k : bv2d (open)(a'range) := (a , b); also works, so doing this you you can use a'range or b'range for the 2nd dimension
d3jones-metrics
@d3jones-metrics
Which would be a way of clarifying what you want, I agree.
But if our poor little aggregate has to stand on its own two feet without any help from outside, what does it say?
Marlon James
@marlonjames

2019 LRM 9.3.3.1

The type of an aggregate shall be determinable solely from the context in which the aggregate appears,
excluding the aggregate itself but using the fact that the type of the aggregate shall be a composite type. The
type of an aggregate in turn determines the required type for each of its elements.

d3jones-metrics
@d3jones-metrics
Which implies that this should be a hard error.
Jim Lewis
@JimLewis
The type of the aggregate is bv2d since that is the type you specified in the constant declaration. What you are trying to sort out is the subtype of the object.
DrPi
@drpi:matrix.org
[m]
bv2d is a array of a array so you should initialize it with := (a)(b) Note : := (a & b) was a really stupid answer ☹️
Marlon James
@marlonjames

I think this covers it:
A subaggregate is a "(n–1)-dimensional array or array aggregate", so a and b are subaggregates in (a, b).
In 9.3.3.3:

[...] For a multidimensional aggregate of dimension n, a check is made that all (n–1)-dimensional subaggregates have the same bounds. It is an error if any one of these checks fails.

Are these equivalent?
type bv1d1d is array(0 to 3) of bit_vector(0 to 3);
type bv2d is array(0 to 3, 0 to 3) of bit;
i.e., are they both two-dimensional arrays, or is bv1d1d a one-dimensional array with element type of bit_vector(0 to 3)?
Richard Head
@trickyhead_gitlab
Your 2nd statement is true - its a 1d and 2d array type
2+-d array types cannot be sliced
tgingold
@tgingold
I think this is an area where there are bugs in the LRM. a & b is not forbidden according to the LRM, but nobody knows what the bounds are.
Marlon James
@marlonjames

Wouldn't it follow

Otherwise, the direction of the index range of the aggregate is that of the index subtype of the base type of the aggregate.

and then

the leftmost bound is given by S'LEFT where S is the index subtype of the base type of the array. [...] the rightmost bound is determined by the direction of the index range and the number of elements.

bradleyharden
@bradleyharden:matrix.org
[m]

@LarsAsplund

My initial response to this would be to implement your design more like an RTL state machine.

Yes, I thought of this. I just hate writing things in an RTL style when it's not RTL. I find it much easier to express behavior concisely when I can use wait statements.

Jim Lewis
@JimLewis
@bradleyharden:matrix.org There was once a coding style for statemachines that used multiple wait statements. For reset, it had the same flaws that you are running into.
Lars Asplund
@LarsAsplund
@bradleyharden:matrix.org I know,, it hurts. OTOH, it's just the top level structure that resembles RTL. Everything within that can be extremely non RTL if that is better. Also, it doesn't have to trigger on rising edge of a clock. There can be other events driving the main loop.
bradleyharden
@bradleyharden:matrix.org
[m]
Yeah, that's a good point. Maybe I'll give it a try and see how it turns out. Do you have any examples of something you've written like that LarsAsplund (Lars Asplund):?
Jim Lewis
@JimLewis

@bradleyharden:matrix.org One thing that can be done sequentially, but I think is easier in an "RTL-like" statemachine is a UART receiver. One advantage of a VC using "RTL-like" techniques, especially when they are as easy as behavioral code, is that it is easier for someone with only RTL experience to understand and modify the VC. In verification, I try to focus on the readable coding style that solves the problem.

Conciseness is important, but I think readability is more important. For example, a very talented student in one of my VHDL classes decided he was going to code a simple statemachine using conditional assignment. He was probably in simulation faster than anyone else, but then encountered a bug. Spent 15 minutes debugging, then asked for help. I suggested a process. It took him 5 minutes to rewrite it using case and if - and then it worked first time. Certainly was not as concise, but it was significantly more readable.

Lars Asplund
@LarsAsplund
@bradleyharden:matrix.org I've also done some analog modelling including a real power port and in those cases I've treated it as an asynchronous input. When you bring all events you had in your original wait statements into a single wait statement, along with the power event, you need some new code to separate them from each other. In the simplest case that is just a long if-elsif statement where each (els)if line handles one event in order of priority. The power event would have the highest prio. More likely you will also need a state to consider. You can handle that state in the elsif conditions or you can flip things around and only have the power event in the if statement condition and then, in the else branch, start with a case statement based on the state variable. Another option is to have the state in the wait statement expression. The cleanest approach depends on your application