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Patrick Lehmann
@Paebbels
@trickyhead_gitlab the problem with VHDL is types are equal if the name of a type is equal.

When you define this:

type line1 is access string;
type line2 is access string;

you get 2 incompatible types.

Thus you need to handover the access type to the protected type, entity or package as a generic type, so you can use it internally as access type or extract from it it's designated type.
To simplify your code, you can remove the designated_type generic, because the access_type holds all needed information.
See the example given in P2 in the LRM.
Patrick Lehmann
@Paebbels
package P2 is
  generic (
    type access_type is access type is private
  );

  alias designated_subtype is access_type'DESIGNATED_SUBTYPE;
end package;
architecture A of E is
  package I2 is new P2
    generic map (
      access_type => line
    );
begin
end architecture;
Richard Head
@trickyhead_gitlab
but why cant the type be formed in the generic region, if a type is left "open" . There is no object created yet, hence is doesnt have to have a value like a normal generic. Also, simply writing type t; is legal as a forward type declaration, but it requires the complete type at a later point in the same unit
I am aware that no connecting the access type makes a brand new type and its not compatable, and thats my point - why shouldnt you be able to do this? inside the package (or other region) you have no care or knowledge of what the type actually is. You cannot have code that is conditional based on type.
Jim Lewis
@JimLewis
@trickyhead_gitlab
Why not just:
package P2 is
generic (
  type designated_subtype
 );
  type fred is access designated_subtype ;
I think you have a choice, either the access type is a type externally defined and you need to create a package that uses it - or - the type is an internally defined type that is unique.
I don't think you can have either depending on how you use it.
Patrick Lehmann
@Paebbels
@trickyhead_gitlab but then you're at the solution @JimLewis provided, right?
Just the type and the definition of the access type is inside the package or protected type.
Richard Head
@trickyhead_gitlab
Next VHDL 2019 question - should a subtype be able to define the generic map of a generic protected type?
Patrick Lehmann
@Paebbels
protected types get instantiated like a package instantiation.
type tricky_pt is new protected pt
  generic map (
    ....
  );
It's a (new) type, and no subtype, because instances of PT are not compatible to each other.
Richard Head
@trickyhead_gitlab
Yes - I read more - you cannot subtype a protected type because a protected type instantiation becomes it's own distinct type. I guess that avoids having "similar" protected types and dodgy casting
Patrick Lehmann
@Paebbels
yes :)
Benedikt J
@beja.65536_gitlab
Hi everyone, is there an example for using the GHDL plugin in Yosys with multiple files? So far, I found a couple of examples but all use a single VHDL file. If I try to add multiple files the usual way (first analyse them via ‘-a’, then elaborate via ‘-e’), I get an error message that option ‘-a’ is not supported.
xiretza
@xiretza:xiretza.xyz
[m]

either create a library file first, then run ghdl-yosys-plugin on that:

ghdl analyze file1.vhdl file2.vhdl subdir/file3.vhdl
ghdl elaborate topentity
yosys -m ghdl -p 'ghdl topentity'

or run ghdl-yosys-plugin directly on the files, without creating a library file:

yosys -m ghdl -p 'ghdl file1.vhdl file2.vhdl subdir/file3.vhdl -e topentity'

in general, the yosys ghdl command is equivalent to invoking the ghdl binary as ghdl --synth.

eine
@eine

Actually, there is another solution in-between:

ghdl analyze file1.vhdl file2.vhdl subdir/file3.vhdl
yosys -m ghdl -p 'ghdl -e topentity'

That is useful if the files are analysed in a library different to the top-level, but you don't care about the logical lib name of the top-level:

ghdl analyze --work=designlib file1.vhdl file2.vhdl subdir/file3.vhdl
yosys -m ghdl -p 'ghdl toplevel.vhd -e topentity'
Furthermore, we have discussed about supporting a single line syntax which allows defining multiple libraries at once. That would work for both synthesis and elab-run.
eine
@eine
So maybe (NOT SUPPORTED YET):
# Synthesis
yosys -m ghdl -p 'ghdl --work=designlib file1.vhdl file2.vhdl subdir/file3.vhdl --work=anyother toplevel.vhd -e topentity'

# Analysis and Elaboration
ghdl -a \
  --work=designlib file1.vhdl file2.vhdl subdir/file3.vhdl \
  --work=anyother toplevel.vhd testbench.vhd \
  -e topentity

# elab-run
ghdl elab-run \
  --work=designlib file1.vhdl file2.vhdl subdir/file3.vhdl \
  --work=anyother toplevel.vhd testbench.vhd \
  -e topentity \
  --wave=mywave.ghw
Benedikt J
@beja.65536_gitlab
Many thanks to both of you! I’ll give it a try and let you know if it worked :-)
d3jones
@d3jones
LRM 2019 12.3: "Within the specification of a subprogram, every declaration with the same designator as the subprogram is hidden." Can someone provide an example showing hiding due to this requirement? Everything I try in GHDL seems to compile without complaint.
Is this legal?
entity test is
end test;

architecture rtl of test is

    function f return real is
        function f return real is
        begin
            return 3.14;
        end f;
    begin
        return f;
    end f;
begin
    process
    begin
        report real'image(f);
        wait;
    end process;
end rtl;
Patrick Lehmann
@Paebbels
If the outer f wouldn't be hidden, it would call it self recursively.
tgingold
@tgingold
Something like procedure p (arg : integer := arg);, where arg is already declared.
d3jones
@d3jones
How is 12.3 applicable here? arg does not have the same designator as any subprogram.
d3jones
@d3jones
And this is already illegal by LRM 2000 4.3.2.1. I cannot find equivalent text in 2019 LRM.
tgingold
@tgingold
Sorry. So something like:
  function f return real;
  function f return integer is
  begin
    return integer(real'(f));
  end f;
Lars Asplund
@LarsAsplund
A bit of history. Had a discussion on LinkedIn today with Cliff Berg who is a co-founder of https://www.agile2academy.com, an author of books about Agile and generally involved in the topic. Turns out that he has a background in VHDL.
I was on the team that created VHDL. I was probably the first person to actually write VHDL, since my task on the team was to write VHDL and see how usable it was.
Obviously he thought it was useful enough so here we are....
Jim Lewis
@JimLewis
@LarsAsplund Did you mention to him that the VHDL WG would welcome his participation :)
OneWingedShark
@OneWingedShark_gitlab
@d3jones - :point_up: July 20, 2021 7:48 AM - Your nested F-function looks to me like it would be an ambiguous call and, if it is, should be illegal.
Lars Asplund
@LarsAsplund
@JimLewis I did not. I think he went on to Java shortly after and then management. A lost soul 😀
d3jones
@d3jones
@OneWingedShark_gitlab possibly true, but GHDL accepts it, and reports 3.14, without complaint.
Which is why I was having so much trouble with that rule. It is not clear what "Within the specification of a subprogram" modifies. I may very well file a PR on this.
OneWingedShark
@OneWingedShark_gitlab
@d3jones - That's a good idea.
Simon Richter
@GyrosGeier_gitlab
Hi
I'm trying to simulate a board that contains two FPGAs that talk to each other over a bidirectional bus
so I'd like to simulate transport delays for two inout ports that are connected together
obviously, signal u1_io, u2_io : std_logic_vector(15 downto 0); followed by u1 : one port map(io => u1_io); u2 : two port map(io => u2_io); u1_io <= transport u2_io after 10 ps; u2_io <= transport u1_io after 10 ps; is not the way to go
Simon Richter
@GyrosGeier_gitlab
The full simulation has three components connected together on the bus, and I'd like to validate the bus turnaround timing at each boundary
Simon Richter
@GyrosGeier_gitlab
http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/BidirectionalConnections looks interesting, especially the 'others attribute: u1_io <= transport u2_io'others after 10 ps; u2_io <= transport u1_io'others after 10 ps; sounds like a reasonable syntax, but I'm not sure how well that would translate to three drivers
Jim Lewis
@JimLewis
Like I replied on https://electronics.stackexchange.com/questions/579531/modeling-bidirectional-propagation-delays, I think you need to get access to the tristate controls. Unfortunate it internal to an encrypted IP. Maybe you can work with your vendor to either get them to add configurable delays or to have them put the tristate IO outside of the encryption in their IP.