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Lars Asplund
@LarsAsplund

@JimLewis

@LarsAsplund @umarcor @Paebbels Did you see that ARM came up with new terminology.

Didn't see that but I was expecting it to happen sooner or later. This was maybe a bit sooner than I though.

Lars Asplund
@LarsAsplund

@umarcor

Dear Colleague Letter: CISE RFI on Semiconductor Research and Education
https://www.nsf.gov/pubs/2021/nsf21112/nsf21112.jsp
/cc @JimLewis @GlenNicholls @LarsAsplund @Paebbels @ktbarrett

Interesting!

Jim Lewis
@JimLewis

@ktbarrett in today's VHDL meeting, Unai pointed me to your earlier post here: https://gitter.im/vhdl/General?at=60df3a674e325e6132b72b8f

What you are talking about sounds like tagged records. In the late 90's Peter Ashenden and some folks from Univ Cincinatti did a proposal called Suave. One of the things Suave added was tagged records. Ada has them. Ada also had protected types. Two different things.

When I first read tagged records, that is something that even engineers without an OO programming background can get their heads around.

I would be interested in seeing tagged records make it into a future revision of VHDL. I have many/most of the papers that were written. They just need to be sorted and organized - perhaps into what is unique material and what is a repeat.

That said, the more I use protected types the more I like them - however it is an acquired taste.
Kaleb Barrett
@ktbarrett

@JimLewis Thanks for the response! I read the paper on SUAVE and there are a lot of things I do like.

  • encapsulation of implementation using packages
  • creating subtypes of custom types
  • supporting dynamic dispatch on subtypes
  • generics (though they did not address constraining generics)

However, I'm not a fan of inheritance. I think that subtype assertion and implementation reuse should be provided as separate language features.

Is there still consideration on bringing some of these features into VHDL?
Jim Lewis
@JimLewis
Someone would need to do the work.
nobodywasishere
@nobodywasishere:eowyn.net
[m]
When are the meeting times again? I might be able to attend them going forward depending on when they are. I don't have much to contribute to them (yet) but I just want to listen and be a part of it.
Kaleb Barrett
@ktbarrett
Site registration doesn't seem to be working? It just takes me to the log in.
Marlon James
@marlonjames
Pinging @umarcor
Unai Martinez-Corral
@umarcor
@ktbarrett, what do you mean with "site registration"? Are you trying to register in TWIKI by following http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/HowToAddToTwiki?
That is manual, and it needs to be done by an admin in TWIKI (Jim, me, don't know who more).
Please, you or anyone willing to have a TWIKI user, send me your First name, Last name, an e-mail address and a Country. I will create the user for you, and you'll get a notification.
Actually, we are moving most of the activity to GitLab, so the TWIKI access is not very useful, except for the Private Documents sections, where we have PDF and DOCX versions of the LRMs.
Anyone willing to help with the LRM conversion to LaTeX should have access, since copying from DOCX is easier than the PDF.
(thanks @marlonjames)
Unai Martinez-Corral
@umarcor

When are the meeting times again? I might be able to attend them going forward depending on when they are. I don't have much to contribute to them (yet) but I just want to listen and be a part of it.

@nobodywasishere:eowyn.net, typically every two weeks. During 2020 and 2021, it was on thursdays. Now we changed it to TUESDAYs. It's 11AM pacific time, 20:00 Central European Time, 19:00 in the UK (might change when some countries change summer/winter time before others).
During this summer, we met every three weeks. The last two meetings and the next one are weekly. Therefore, the period is kind of arbitrary.
If you, or anyone, has some topic to discuss in a meeting, please bring it in the GitLab repository. Thre are labels for marking issues/MRs.
We can also schedule meetings other days and at other times. We meet at 11AM/20:00 because that fits the "usual suspects". Yet, every once in a while we meet to work on something specific.

Marlon James
@marlonjames
@umarcor I think the main reason to have a TWIKI account at this point is for access to the dial in info. If we want to move that to one of the private GitLab repos, we wouldn't need to require a TWIKI account to participate.
Unai Martinez-Corral
@umarcor
@marlonjames, that is so obvious and still I had not realised :embarrassed:
We don't have any private repo which fits that purpose, though...
Maybe some GitLab-Jitsi (or gotomeeting, or zoom) integration exists which inherits access permissions from the gitlab org.
ktbarrett
@ktbarrett:matrix.org
[m]

Lol. I was just about to say if you are moving away from the TWiki, you could just move to private repos and Gitlab teams.

I know TFS, Azure, and Teams have some amount of integration. Github has "teams" and team wikis and chat, no video/voice chat though.

Jim Lewis
@JimLewis
@umarcor @marlonjames we still need a place to organize the protected documents. OTOH, maybe the protection would be better as with TWIKI if you know the direct link to the doc, you don't need a password anymore.
When you get an IEEE account (apparently no membership required), you also get an email with it and the Google meetings (what ever they call it). At least, I don't think there is an IEEE membership required for the email and meetings capability.
Richard Head
@trickyhead_gitlab

Hi All. VHDL 2019 question. Can an array using an index (natural range <>) be assigned to a generic array who range is declared as (integer range <>) ?
so if I had this generic:

generic (
      type element_array_t is array(integer range <>) of type is private;
    );

Could I assign std_logic_vector as the generic array type? what would element_array_t'left return ?

Kaleb Barrett
@ktbarrett
Is there any way to associate constants with a record? Imagine for a register interface you could do something like the following:
type Register is record
    constant INFO : RegisterInfo;
    signal data : std_logic_vector;
    signal be : std_logic_vector;
end record Register;
Patrick Lehmann
@Paebbels
elements of a record have no object class. When an object is created from a record type, all subelements have the same object class.
Kaleb Barrett
@ktbarrett
Also, is there a way to enforce additional constraints on record parameterization using an assert? I could imagine maybe you could put an assert in the record definition, or perhaps create a metafunction that can return a type, and the assert is in the body?
Patrick Lehmann
@Paebbels
you can attach constant meta information via user defined attributes to objects, types, ...
Kaleb Barrett
@ktbarrett
What about on entity instances? I would really like to be able to make constant information from an entity as instantiated available to the instantiator.
T. Meissner
@tmeissner
@ktbarrett There are some issues at Gitlab regarding such things. I remember of one to add things like asserts to com,posite types like records.
But I don't find the gitlab issue at the moment
Richard Head
@trickyhead_gitlab
@ktbarrett Allow constants in composite subtypes: IEEE-P1076/VHDL-Issues#242
@ktbarrett Asserts in record types: IEEE-P1076/VHDL-Issues#99
These are two existing proposals - give them a thumbs up if you like them.
Kaleb Barrett
@ktbarrett
@trickyhead_gitlab Thanks for the links. The first one isn't quite what I was looking for. I was looking for a compile-time value in the record.
I see the issue with what I asked for. It's the same issue with out generics. The language (as do many others, like C++) segregate compile-time and runtime code and data sections. Its a huge expressivity problem and not one I expect to ever be solved.
Jim Lewis
@JimLewis
@ktbarrett Records don't have signals or constants. However, if RegisterInfo is a scalar, then you could put a range constraint on it that only allows one value. :)
type Register is record
    INFO : integer range 2 to 2;
    data : std_logic_vector;
    be : std_logic_vector;
end record Register;
While it is not a constant, it will default to 2, and will only allow the value 2 to be written to it.
Jim Lewis
@JimLewis
Ranges can be used with any scalar, including enums
Patrick Lehmann
@Paebbels
even the examples in the presentation have been copied from the OSVVM classes
m-kru
@m-kru
Are there plans to introduce something like "library nesting" in VHDL?
Kaleb Barrett
@ktbarrett
@JimLewis RegisterInfo would be a compile-time value, as the register meta information would guide some generates (in the system I'm working on). Right now the type is split into a constant array of register info records and a runtime array of register interface records. I was wondering if I could possible combine them, which would make certain things easier. Even if constants were supported in records, because generics and ports are separated on entities there really isn't a good way to pass that in.
@Paebbels Who is "they"?
Patrick Lehmann
@Paebbels
Argh, I hit a bug of Gitter, sometime it shows messages from other chats here ...
Unai Martinez-Corral
@umarcor

Are there plans to introduce something like "library nesting" in VHDL?

@m-kru, do you mean the names of two libraries being aliased?

4 replies
Jim Lewis
@JimLewis
@m-kru You would be welcome to participate and work on that issue.
Jim Lewis
@JimLewis
@ktbarrett Have you looked at Ada and see if they have a solution for this? I think a discriminant on a record can set an initial value and I think under some conditions it can be static. I would have to read it again. In the mean time, maybe you want to look at that and see if it is suitable.
Kaleb Barrett
@ktbarrett
@JimLewis It looks like record discriminants are similar to what I'm asking for, but they suffer the same lack of expressivity as non-type templates in C++. For example, how do you create an array of heterogenously discriminated types? That's my use case after all.