When are the meeting times again? I might be able to attend them going forward depending on when they are. I don't have much to contribute to them (yet) but I just want to listen and be a part of it.
@nobodywasishere:eowyn.net, typically every two weeks. During 2020 and 2021, it was on thursdays. Now we changed it to TUESDAYs. It's 11AM pacific time, 20:00 Central European Time, 19:00 in the UK (might change when some countries change summer/winter time before others).
During this summer, we met every three weeks. The last two meetings and the next one are weekly. Therefore, the period is kind of arbitrary.
If you, or anyone, has some topic to discuss in a meeting, please bring it in the GitLab repository. Thre are labels for marking issues/MRs.
We can also schedule meetings other days and at other times. We meet at 11AM/20:00 because that fits the "usual suspects". Yet, every once in a while we meet to work on something specific.
Lol. I was just about to say if you are moving away from the TWiki, you could just move to private repos and Gitlab teams.
I know TFS, Azure, and Teams have some amount of integration. Github has "teams" and team wikis and chat, no video/voice chat though.
Hi All. VHDL 2019 question. Can an array using an index (natural range <>) be assigned to a generic array who range is declared as (integer range <>) ?
so if I had this generic:
generic (
type element_array_t is array(integer range <>) of type is private;
);Could I assign std_logic_vector as the generic array type? what would element_array_t'left return ?
type Register is record
INFO : integer range 2 to 2;
data : std_logic_vector;
be : std_logic_vector;
end record Register;
RegisterInfo would be a compile-time value, as the register meta information would guide some generates (in the system I'm working on). Right now the type is split into a constant array of register info records and a runtime array of register interface records. I was wondering if I could possible combine them, which would make certain things easier. Even if constants were supported in records, because generics and ports are separated on entities there really isn't a good way to pass that in.
4 replies
I suppose discriminant mutation would also be excluded.
So you would be allowed to use only static discriminant. Fine.
But then, you can already use a record with a first element acting as the discriminant, and all the elements you need. This fake discriminated type is less compact than a real one and don't provide check on existing elements.
Hi! I've got a problem with a generic procedure.
procedure convert_to_type generic (type t)
parameter (constant s : in string; variable v : out t) is
begin
v := t'value(s);
end procedure;
procedure parse(constant s : in string) is
type value_t is (V1, V2, V3, V4);
procedure convert_to_value is new convert_to_type generic map (t => value_t);
variable v : value_t;
begin
convert_to_value("V1", v);
end procedure;Modelsim reports the following error Attribute "value" requires a scalar type mark prefix.
Is there a way to tell VHDL that the t type is going to be a scalar ? Or any tricks to overcome this issue ?
(I know I could have used directly value_t'value(v) but in my code, it's more complex that this MWE)
Thanks
@std-max Unfortunately not in VHDL 2008. on the convert_to_type procedure, type t could be literally any type - scalar, composite or access. So t'value cannot be used because it would be illegal for composite or access types. VHDL 2019 fixes this by allowing you to specify types to be scalar or composite (or just anything).
For example:
procedure some_proc generic( type t is array(natural range<>) of (type is <>) )Here, you are specifying that the type must be array of a scalar type.
