VHDL/General

Discussions about the VHDL language, VHDL tools chains and frameworks around VHDL.

Unai Martinez-Corral

@umarcor

We might want to discuss about ghdl/ghdl#980 in the VASG, since that is the only public discussion related to this topic I am aware about.

The motto that VHDL is backwards compatible back to 87 is nice, but it is not true anymore. We might want to acknowledge it in the LRM.

Kaleb Barrett

@ktbarrett

@d3jones-metrics I think you might misunderstand what "deprecated" means. It does not mean removed. It tends to mean it remains, but is discouraged in some way. Perhaps it prints a frowny face every time you use. Or perhaps it reports to the same entity that kills kittens when you use from module import * in Python.

Jim Lewis

@JimLewis

WRT IEEE, there is one revision, the current balloted revision - VHDL-2019.

Going further, shared variables of an ordinary type are special - when they were added the LRM noted they were a temporary feature and would be replaced in the next revision - and that indeed did happen.

Richard Head

@trickyhead_gitlab

maybe we could just propose shared variables can be any type? In the same way 2008 gave in to std_logic_unsigned and added numeric_std_unsigned and also rolled std_logic_textio into the standard?

Unai Martinez-Corral

@umarcor

WRT IEEE, there is one revision, the current balloted revision - VHDL-2019.

@JimLewis that is ignored by the majority of the industry, and neither IEEE nor VASG can do anything to fix that in the short or mid term. We might acknowledge it, at least.

Jim Lewis

@JimLewis

Adding textio support for std_logic_vector, unsigned, signed, ufixed, sfixed, and float were a value add to the language.

Adding numeric_std_unsigned was also a value add to the language - since it has consistent subprograms WRT numeric_std.

What is the value of supporting shared variables of an ordinary type? For the uses I have seen, there is a better use model using either protected types or something else - see my linked in post: https://www.linkedin.com/pulse/vhdl-shared-variables-protected-types-memory-modeling-jim-lewis/

Richard Head

@trickyhead_gitlab

std_logic_textio is nothing more than an empty package in 2008 and purely there for backward compatibility with code that used it in previous standardards. The actual textioIO was added to the packages that defined the types

Jim Lewis

@JimLewis

Yes. And?

What that did was allow people who were using the old package to keep using it and at the same time get the upgraded version.

Richard Head

@trickyhead_gitlab

Im trying to ask - why was this put in to maintain backwards compatability with non-standard code, yet doing the same with non protected type shared variables is an issue?

numeric_std_unsigned was only added, IMO, because people were continuing to use, and refused to migrate away from std_logic_unsigned. Again, this is basically the same reason that std_logic_textio was added to the standard

Jim Lewis

@JimLewis

Currently in the LRM, the word share variable is often used in the context of its usage with a protected type. So to re-add shared variables of an ordinary is a non-trivial, time consuming change - that is potentially error prone. Not something I would be personally willing to take on.

Jim Lewis

@JimLewis

I like numeric_std_unsigned in RTL code and would require it in a design team - not to intentionally use it, however, my concern is that it is easy for someone to mistakenly use > with std_logic_vector. This can result in RTL and GATE implementation mismatches. This is a subtle bug that is hard to find - even with an experienced review team. However, if one were to include numeric_std_unsigned then > always has a consistent meaning in both RTL and GATE - and it is easy to review for - did they include the package or not. Hence, using numeric_std_unsigned makes something that is a design bug into a methodology mistake.

@trickyhead_gitlab Do you have a use model where you want to use shared variables of an ordinary type?

Brian Padalino

@bpadalino

this all stemmed from vivado inferring dual port bram and using a shared variable to do it?

Jim Lewis

@JimLewis

@umarcor There is no longer a reason for a user to use multiple versions of the language. The reason VHDL-93 was used is that historically was the subset of the language used for RTL. Hence, it was a lint tool that made sure you did not introduce something the synthesis tool could not handle. However, you should be able to compile 93 RTL code in 2008 and have it work the same way.

A simulator that only supports one version would work fine. Even with the lint check. First compile the RTL for 93 as a lint check. Then compile it for 2008 and simulate it with other 2008 code.

@bpadalino And from UVVM using shared variables of an ordinary type, suppressing the error messages, and telling their community that this is a proper thing to do. Then claiming that implementing verification component interfaces is hard to do in any other way - when there are methodologies such as VUnit and OSVVM (as well as other private methodologies) that do not use shared variables of an ordinary type. We will see. They have a new release coming up in October - maybe they fixed it.

Brian Padalino

@bpadalino

i see .. i haven't seen/used UVVM .. interesting they make such extensive use of it

Unai Martinez-Corral

@umarcor

@JimLewis, how to simulate an IP core using shared variables of an ordinary type with a verification framework using VHDL 2008 (or 2019) features?
That's the most common use case we find in GHDL (using VUnit, OSVVM...).

It's not possible to compile the framework using 93.
It's not possible to compile the IP using strict 2008.
Therefore:
Linting or synthesis using strict 93 is possible.
For simulation, non-strict 2008 is required, where non-strict means "analyse some constructs as if it was not 2008 but an earlier revision".

A simulator with strict 2008 support cannot handle that use case; it forces the IP to be updated.

Jim Lewis

@JimLewis

@umarcor strict2008 sounds appropriate.

Unai Martinez-Corral

@umarcor

@JimLewis, then maybe it is legit to ask shared variables of ordinary type to be introduced in the LRM again, since they need to be supported anyway by any strict2008 simulator.

Jim Lewis

@JimLewis

@umarcor Asking is always ok. However, speaking for myself as an individual, I would neither vote in favor of such a proposal nor work on it. There are more high value items to work on then supporting things that should have never been done. I would argue that none of the code that uses these constructs was written before VHDL-2000 when it became illegal. Simulators have always at a minimum warned that such an item was illegal. Perhaps using the word warning was a little to subtle for people - maybe they should have used suppressed warning

@umarcor You keep saying strict 2008. Lets make a small correction. It was 1076-2000/2002 that made shared variables of a ordinary type illegal. So anything that is strict 2000, does not allow it. It was the prior version (1076-1993) where they were added and it was noted that they were added as a temporary feature.

Jim Lewis

@JimLewis

@umarcor

how to simulate an IP core using shared variables of an ordinary type with a verification framework using VHDL 2008 (or 2019) features?

What is the use model for this? If they want to use strict2008, then they should fix their code, right?

Lars Asplund

@LarsAsplund

@ktbarrett With "deprecate" I actually meant "remove" but there could also be an intermediate step where a warning is issued. I've used that myself for VUnit. What I'm challenging is the idea that because someone might be using an old feature it has to maintained. Dependency on old features make progress harder and in worst case it prevents progress. I also think we need to recognize that companies not willing to take the cost of updating their code base when adopting a new standard translate to additional unpaid time for the maintainers of VHDL. If you really can't change your code you can always stick with the old standard or keep that code separate from the rest.

Unai Martinez-Corral

@umarcor

What is the use model for this? If they want to use strict2008, then they should fix their code, right?

@JimLewis, unless the code was bought from a third-party and there is no budget for having it updated/fixed.

I keep saying "strict 2008" because I believe that the usage of shared variables of an ordinary type should be an error, not a warning. In order to allow it, the strictness needs to be relaxed. Some might argue that it is not an error in 2008 and 2019. That might be correct. However, as Lars is suggesting, at some point a deprecated and "illegal" feature should be removed. If deprecated features are not removed, the LRM needs to account for backwards compatibility exceptions.

Kaleb Barrett

@ktbarrett

@LarsAsplund I think most SW projects today give people a grace period where deprecation warnings are given before the feature is removed. Of course, the release cycle on those projects is far more frequent than VHDL language releases. In this case it doesn't seem to be breaking anything by leaving it in and deprecating it? Bad ideas can always cause warnings. Unless it totally broken and impeding progress, removal isn't strictly necessary. Non-essential removals should come after the community has reacted to deprecation status or after some amount of time that is agreed upon beforehand. For example, when Python does deprecations-pending-removals, they tell users exactly what release the feature will be removed in and what to use instead. If you don't compensate in time, it's your fault. Maybe if VHDL had a shorter development cycle (3 years like C++?), language could be added about how tools should handle deprecations and could state features are deprecated for 1 language revision and removed in the next, which gives users a pre-determined amount of time to react.

Jim Lewis

@JimLewis

@umarcor They were REMOVED! in VHDL-2000. They were added in VHDL-1993, so they are only legal for that version and no other.

Adding them in not a simple matter of moving them from the deprecated list to the supported list. It will take going though the current revision, clarifying every usage of shared variable in the LRM to indicate it refers to a shared variable of a protected type. Then going back to the VHDL-1993 revision and reviewing the text for shared variables and all the restrictions of their usage by VHDL-1993 and restoring that to the LRM with edits to clarify that they are for shared variables of an ordinary type.

Without compelling use models, I don't see the point.

Jim Lewis

@JimLewis

@Kaleb - When VHDL added shared variables of an ordinary type, it was noted that they were a temporary feature and would be replaced in the next revision.

At this point, it is 21 years after the feature was removed. :)

Unai Martinez-Corral

@umarcor

@JimLewis, I'm not arguing that they were or were not removed. I'm showing a counterexample of:

A simulator that only supports one version would work fine. Even with the lint check. First compile the RTL for 93 as a lint check. Then compile it for 2008 and simulate it with other 2008 code.

A simulator which supports VHDL 2008 and only VHDL 2008 cannot handle RTL 00. RTL 00 cannot be "compiled for 2008", but it needs to be some 2008-compat mode.

Because it is not possible for a VHDL simulator to support the latest revision and only the latest revision, we should have an specific explanation/section in the LRM for that.

Alternatively, if we expect the simulator to handle RTL 00 specific constructs as a warning when using 2008, then we are explicitly requiring any simulator to support all previous revisions (not only one).

Jim Lewis

@JimLewis

What is RTL 00? I know of 1076.6-1999 and 1076.6-2004 (worked on both).

Unai Martinez-Corral

@umarcor

RTL is "VHDL code written in 2000, when using shared variables of ordinary type was legal".

Jim Lewis

@JimLewis

You should use RTL 93. Shared variables were deprecated and removed by VHDL-2000

There are other correct ways to create memories without using shared variables as illuminated in my paper.

Unai Martinez-Corral

@umarcor

It's irrelevant, in the sense that this is a discussion from a logic (philosophical) perspective. Specific versions and features are just an example to illustrate the conflict.

Jim Lewis

@JimLewis

It is relevant. You are propagating a myth that shared variables were supported for more than 7 years.

Unai Martinez-Corral

@umarcor

Not at all. I'm propagating that shared variables were officially supported at some time. Even if it was one month.

I came when they were deprecated already and I have always avoided their usage, so I have no need for them at all.

However, I am claiming that VHDL is not completely backwards compatible and older sources cannot be analysed using a modern revision of the language. That holds almost correct, but not completely true.

Jim Lewis

@JimLewis

On the same note, Xilinx promoted std_logic_arith - it may still be in their documentation. Should we be considering that for standardization too? It is already in the IEEE library.

How do we get FPGA vendors more vested in the standards process?

Unai Martinez-Corral

@umarcor

I don't think so. I think that neither of the features we are discussing about should be introduced in the standard. Conversely, I believe it is time to strongly deprecate (aka remove) them. Strong deprecation means making it explicitly that backwards compatibility is not an strict feature of the VHDL language any more.

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