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  • Feb 03 02:13

    umarcor on keep-compiling

    ci: use the built-in '--keep-co… (compare)

  • Feb 03 02:12

    umarcor on cosim

    cosim/dpi-ffi: add 'vhdpi_ghdl.… cosim/dpi-ffi: add VHDPI_Test (compare)

  • Feb 03 01:56

    umarcor on cosim

    WIP setenv (compare)

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  • Feb 03 01:54

    umarcor on cosim

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  • Feb 03 01:52

    umarcor on main

    WIP envvars (compare)

  • Feb 03 01:50

    umarcor on cosim

    WIP envvars (compare)

  • Feb 02 23:13

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  • Feb 02 23:13

    umarcor on main

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  • Feb 02 23:13

    umarcor on cosim

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  • Feb 02 23:10

    umarcor on master

    cosim/dpi-ffi: create subdir 'g… cosim/dpi-ffi: fix compilation … cosim/dpi-ffi/ghd-vffi: use VUn… and 2 more (compare)

  • Feb 02 22:58

    umarcor on cosim

    ci: add workflow CoSim cosim/dpi-ffi: add README (compare)

  • Feb 02 22:45

    umarcor on cosim

    ci: add workflow CoSim cosim/dpi-ffi: add README (compare)

  • Feb 02 22:43

    umarcor on cosim

    cosim/dpi-ffi: create subdir 'g… cosim/dpi-ffi: fix compilation … cosim/dpi-ffi/ghd-vffi: use VUn… and 2 more (compare)

  • Oct 05 2021 13:29

    umarcor on top-subtype

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  • Oct 05 2021 13:28

    umarcor on master

    2008: ad tb_top_generic_subtype cosim: add ref to aguinet/drago… (compare)

  • Sep 24 2021 20:07

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 24 2021 19:59

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 24 2021 19:54

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 23 2021 01:45

    umarcor on style

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Unai Martinez-Corral
@umarcor
So, the MR is a placeholder. Feel free to pick it and do further tests
sckoarn
@sckoarn
sorry, MR?
merge request ...
Unai Martinez-Corral
@umarcor
It's normative, so it won't be merged until it's discussed in a meeting
MR: Merge Request. Gitlab's equivalent to Github' PR (pull request)
sckoarn
@sckoarn
Yes, ok I had full details of every line from before. I am not at that state yet. Should I wait till I can provide full details?
Mid next week I expect to be done with numeric_bit.
Kaleb Barrett
@ktbarrett
Why is case not a concurrent statement?
when statement chains are super readable.
Brian Padalino
@bpadalino
aren't you able to use when statements outside of a process ?
Kaleb Barrett
@ktbarrett
That's what I'm complaining about. I don't enjoy making when statement chains compared to just writing a case statement
Brian Padalino
@bpadalino
then wrap your case in a process(all) statement
doesn't that solve the issue?
Kaleb Barrett
@ktbarrett

just add more code

Awesome

Brian Padalino
@bpadalino
process(all) case ... end case ; end process; is too much?
the with/select statement is the same as the case except with a slightly different syntax, the same readibility of the case/when, and is concurrent
why is with/select not the solution you want ?
Brian Padalino
@bpadalino
i think the crux of it, from a language standpoint, is that case statements can assign to all sorts of signals .. not just a single one .. so with/select assigns to a single signal .. adding case in a concurrent manner would really screw with that
so if you just prefer reading the case statement, and are only assigning to a single signal, then living with having to write 3 extra lines of code for a style preference doesn't seem like too bad of a compromise
Brian Padalino
@bpadalino
i guess it's just 2 lines since you're wrapping it in a simple process
Richard Head
@trickyhead_gitlab

Why is case not a concurrent statement?

likely for the same reason an if statement is not concurrent

Brian Padalino
@bpadalino
i don't have access to the LRM, but does it say anything about how boolean values are represented when using read or write? can they be uppercase or lowercase and it doesn't matter ?
Richard Head
@trickyhead_gitlab
@bpadalino for implementation details, I look at the GHDL github repo as the LRM doesnt define the implementation on the functions (I think IEEE provides a reference implementation that tools use). GHDL version here will read upper or lower case or any combination of. https://github.com/ghdl/ghdl/blob/dabf31c2b12633033cea5a177f0deefe28c05c9b/libraries/std/textio-body.vhdl#L653
Brian Padalino
@bpadalino
@trickyhead_gitlab thanks .. it seems to write uppercase .. and nvc uses lowercase .. i didn't know if there was a definitive answer .. but it sounds like either
6 replies
@trickyhead_gitlab i was told by @nickg that the LRM appears to say that write for reals in VHDL say to use the exponential if the precision is set to 0 .. but ghdl doesn't seem to do that ?
i wonder if thats an inconsistency .. where real'image() says to not use exponents .. but the write does ..?
Brian Padalino
@bpadalino
i had a little conversation with @johonkanen yesterday, and it was mentioned that he has a repository of some high level synthesizable VHDL modules (https://github.com/hVHDL) that tries to maximize reuse .. and it got me wondering about modern VHDL techniques for (1) verification and validation, (2) synthesis, and (3) maximum reuse
the thought reminds me of what happened with javascript back in the mid 2000's .. where the frameworks got a bit more structured and helpful - improving reuse and giving way to a modern approach to writing javascript code
other than @johonkanen's repo .. has anyone else been writing about this? or have good examples? are there good community guidelines?
Patrick Lehmann
@Paebbels
something like PoC?
Jari Honkanen
@johonkanen
I am currently writing the readthedocs pages https://hvhdl.readthedocs.io in order to make it more easy for someone else to use them in their code.
Brian Padalino
@bpadalino
@Paebbels more than just a proof of concept, but actual designs for synthesis that are portable and reusable? it seems like everyone reimplements their own spi, uart, i2c, etc. but why is that? is it just because it's "easy enough" or is it because the underlying aspects aren't that reusable? @johonkanen has some synthesizable floating point stuff that isn't completely ieee-754 compatible but is very close .. how many vendors are providing completely different floating point implementations that are all pretty obtuse?
2 replies
@Paebbels also thinking about FSM design .. i was taught 1-process, 2-process, and 3-process FSM .. but it was only after being in the world for a while that i came across the gaissler method or structured vhdl design .. is that what is recommended? is it not?
oh, i meant to add in (4) debug .. vhdl allows for global signals .. is it useful to describe those for global debug packages for your designs? most people don't know those exist
Richard Head
@trickyhead_gitlab
@bpadalino I think the issue is that, in the past, anything "open" on the internet has either been "not quite" useful enough or there is no trust in them and the level of support or quality of code is often "questionable". Plus many companies have spent a lot of time and effort building their own they are unlikely to feed them back onto the internet. Then there has generally been the issue that if anything IS good enough, it will have usually only been built to support xilinx or altera/intel. Supporting multiple architectures will require access to multiple tool set which most people simply do not have.
Tool vendors have no interest in making cross platform code as they want to lock you in.
So while cross compiling has existed for many many years for software, more care normally needs to be taken with HDLs, needing more consideration in the design. FPGA designers are usually far more resource conscious than software developers and pushing the speed/area for a design usually means its not easily compatible with another family.
re: Gaissler method - Ive never seen it in "live use". Ive seen more use of HDL disaster which many people agree is a terrible thing
Richard Head
@trickyhead_gitlab
global signals: synth tools will refuse to synth them, hence their lack of use. They only have use in simulation - and now with external names they are more redundant than they once were - plus mentor had signal spy (plus aldec equivolent) which gave you 2008 external name like access to signals within a design.
Back to re-usable frameworks - I think we're having a heyday in Verification - OSVVM, UVVM, VUNIT and CocoTB are all seeing much more use in industry than 5 years ago.
I think a few teams started using UVM and realised that while the return on investment was good with lower bug returns, maintaining a split VHDL/SV+UVM department is just too hard. I certainly went through redundancies where the verification team got the chop first because "RTL engineers can do verification right?" Well turns out their UVM skills are just non existant, so these teams want to keep the level of verification going but with a VHDL based framework (and python is getting popular hence VUnit and CocoTB)
Colin Marquardt
@cmarqu
@bpadalino "PoC" mentioned by @Paebbels in this context means https://github.com/VLSI-EDA/PoC
Brian Padalino
@bpadalino
@cmarqu thanks for the clarification
first time i've heard of it
@trickyhead_gitlab i swear i've been able to synthesize global signals in packages before .. maybe it was just a synplify pro thing ?
Brian Padalino
@bpadalino
some initial criticisms of PoC - they are naming a package PoC with capitalization in a case insensitive language .. some of the words being used in the entities are shortened by 1 letter for no reason .. grnt instead of grant .. randomly looking at a UDP example, seems like lots of vectors and no records for instantiation - https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl#L49 ..
i am unsure if the PoC stuff exemplifies the modern VHDL approach that i think i am advocating for .. i guess, in all honesty, i am wondering if there are general guidelines and a consensus from the VHDL WG or VHDL community in general about best practices for those 4 things i mentioned
here's one i am unsure about .. when declaring std_logic_vector as an input to, say, a RAM module for data .. should you really write a WIDTH generic to supply the width .. or should modern VHDL rely on VHDL-2019 to use in_data'range to supply the output? in an ideal world where the language is actually supported, what is the best practice ?