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Brian Padalino
@bpadalino
the with/select statement is the same as the case except with a slightly different syntax, the same readibility of the case/when, and is concurrent
why is with/select not the solution you want ?
Brian Padalino
@bpadalino
i think the crux of it, from a language standpoint, is that case statements can assign to all sorts of signals .. not just a single one .. so with/select assigns to a single signal .. adding case in a concurrent manner would really screw with that
so if you just prefer reading the case statement, and are only assigning to a single signal, then living with having to write 3 extra lines of code for a style preference doesn't seem like too bad of a compromise
Brian Padalino
@bpadalino
i guess it's just 2 lines since you're wrapping it in a simple process
Richard Head
@trickyhead_gitlab

Why is case not a concurrent statement?

likely for the same reason an if statement is not concurrent

Brian Padalino
@bpadalino
i don't have access to the LRM, but does it say anything about how boolean values are represented when using read or write? can they be uppercase or lowercase and it doesn't matter ?
Richard Head
@trickyhead_gitlab
@bpadalino for implementation details, I look at the GHDL github repo as the LRM doesnt define the implementation on the functions (I think IEEE provides a reference implementation that tools use). GHDL version here will read upper or lower case or any combination of. https://github.com/ghdl/ghdl/blob/dabf31c2b12633033cea5a177f0deefe28c05c9b/libraries/std/textio-body.vhdl#L653
Brian Padalino
@bpadalino
@trickyhead_gitlab thanks .. it seems to write uppercase .. and nvc uses lowercase .. i didn't know if there was a definitive answer .. but it sounds like either
6 replies
@trickyhead_gitlab i was told by @nickg that the LRM appears to say that write for reals in VHDL say to use the exponential if the precision is set to 0 .. but ghdl doesn't seem to do that ?
i wonder if thats an inconsistency .. where real'image() says to not use exponents .. but the write does ..?
Brian Padalino
@bpadalino
i had a little conversation with @johonkanen yesterday, and it was mentioned that he has a repository of some high level synthesizable VHDL modules (https://github.com/hVHDL) that tries to maximize reuse .. and it got me wondering about modern VHDL techniques for (1) verification and validation, (2) synthesis, and (3) maximum reuse
the thought reminds me of what happened with javascript back in the mid 2000's .. where the frameworks got a bit more structured and helpful - improving reuse and giving way to a modern approach to writing javascript code
other than @johonkanen's repo .. has anyone else been writing about this? or have good examples? are there good community guidelines?
Patrick Lehmann
@Paebbels
something like PoC?
Jari Honkanen
@johonkanen
I am currently writing the readthedocs pages https://hvhdl.readthedocs.io in order to make it more easy for someone else to use them in their code.
Brian Padalino
@bpadalino
@Paebbels more than just a proof of concept, but actual designs for synthesis that are portable and reusable? it seems like everyone reimplements their own spi, uart, i2c, etc. but why is that? is it just because it's "easy enough" or is it because the underlying aspects aren't that reusable? @johonkanen has some synthesizable floating point stuff that isn't completely ieee-754 compatible but is very close .. how many vendors are providing completely different floating point implementations that are all pretty obtuse?
2 replies
@Paebbels also thinking about FSM design .. i was taught 1-process, 2-process, and 3-process FSM .. but it was only after being in the world for a while that i came across the gaissler method or structured vhdl design .. is that what is recommended? is it not?
oh, i meant to add in (4) debug .. vhdl allows for global signals .. is it useful to describe those for global debug packages for your designs? most people don't know those exist
Richard Head
@trickyhead_gitlab
@bpadalino I think the issue is that, in the past, anything "open" on the internet has either been "not quite" useful enough or there is no trust in them and the level of support or quality of code is often "questionable". Plus many companies have spent a lot of time and effort building their own they are unlikely to feed them back onto the internet. Then there has generally been the issue that if anything IS good enough, it will have usually only been built to support xilinx or altera/intel. Supporting multiple architectures will require access to multiple tool set which most people simply do not have.
Tool vendors have no interest in making cross platform code as they want to lock you in.
So while cross compiling has existed for many many years for software, more care normally needs to be taken with HDLs, needing more consideration in the design. FPGA designers are usually far more resource conscious than software developers and pushing the speed/area for a design usually means its not easily compatible with another family.
re: Gaissler method - Ive never seen it in "live use". Ive seen more use of HDL disaster which many people agree is a terrible thing
Richard Head
@trickyhead_gitlab
global signals: synth tools will refuse to synth them, hence their lack of use. They only have use in simulation - and now with external names they are more redundant than they once were - plus mentor had signal spy (plus aldec equivolent) which gave you 2008 external name like access to signals within a design.
Back to re-usable frameworks - I think we're having a heyday in Verification - OSVVM, UVVM, VUNIT and CocoTB are all seeing much more use in industry than 5 years ago.
I think a few teams started using UVM and realised that while the return on investment was good with lower bug returns, maintaining a split VHDL/SV+UVM department is just too hard. I certainly went through redundancies where the verification team got the chop first because "RTL engineers can do verification right?" Well turns out their UVM skills are just non existant, so these teams want to keep the level of verification going but with a VHDL based framework (and python is getting popular hence VUnit and CocoTB)
Colin Marquardt
@cmarqu
@bpadalino "PoC" mentioned by @Paebbels in this context means https://github.com/VLSI-EDA/PoC
Brian Padalino
@bpadalino
@cmarqu thanks for the clarification
first time i've heard of it
@trickyhead_gitlab i swear i've been able to synthesize global signals in packages before .. maybe it was just a synplify pro thing ?
Brian Padalino
@bpadalino
some initial criticisms of PoC - they are naming a package PoC with capitalization in a case insensitive language .. some of the words being used in the entities are shortened by 1 letter for no reason .. grnt instead of grant .. randomly looking at a UDP example, seems like lots of vectors and no records for instantiation - https://github.com/VLSI-EDA/PoC/blob/master/src/net/udp/udp_Wrapper.vhdl#L49 ..
i am unsure if the PoC stuff exemplifies the modern VHDL approach that i think i am advocating for .. i guess, in all honesty, i am wondering if there are general guidelines and a consensus from the VHDL WG or VHDL community in general about best practices for those 4 things i mentioned
here's one i am unsure about .. when declaring std_logic_vector as an input to, say, a RAM module for data .. should you really write a WIDTH generic to supply the width .. or should modern VHDL rely on VHDL-2019 to use in_data'range to supply the output? in an ideal world where the language is actually supported, what is the best practice ?
Jari Honkanen
@johonkanen
I think that reuse is most useful when we create as small reusable modules as possible since small things are easier to find use for than large modules. For example hvhdl ram module has a separate read record and its associated interface https://github.com/hVHDL/hVHDL_memory_library/blob/main/fpga_ram/ram_read_port_pkg.vhd this is also used for a lookup table sine https://github.com/hVHDL/hVHDL_math_library/blob/main/sincos/lut_sine_pkg.vhd
Richard Head
@trickyhead_gitlab
@bpadalino definitely didnt work last time I used quartus - I even raised a ticket and they said "NO"
Brian Padalino
@bpadalino
as another example, here is vhdl-2019 trying to make an axi streaming entity where you just hook up the signals that are implemented and don't have to keep either open or drive with 0's the other fields .. https://www.edaplayground.com/x/U6x9
@trickyhead_gitlab huh, interesting .. bummer
Jari Honkanen
@johonkanen
Also the lookup table sine has a separate generator function package for changing the function that creates the contents of the lookup table, thus any function that takes in real numbers from 0.0 to 1.0 and returns values between -1.0 and 1.0 can be used. Currently there are functions for sine and sine with harmonics https://github.com/hVHDL/hVHDL_math_library/tree/main/sincos/lut_generator_functions
Jari Honkanen
@johonkanen
The best way that have come up with is by defining word lengths and any other changeable parts of a module in a separate package. This way the configuration can be defined with the library to which the module is compiled to. For example if 16x1024 and 32x512 rams are required then a package can be defined where these constants are. Then the sources just need to be compiled to the same library with the ram record where the memory is defined and we can add versions of this record by compiling the same sources to different libraries of different names. Since we can change both the functions and the insides of records this way we can add pretty much any functionality to any module.
Brian Padalino
@bpadalino
i mean, that seems like what the tools support .. but it still seems like a lot of effort on the designer side .. we know information about the instantiation - and it can determine the size of the vectors .. the functionality of the architecture can even changed based on what is connected to it without changing generics .. which could be a point of misconfiguration, right ?
Patrick Lehmann
@Paebbels
@bpadalino like other libraries, PoC has a history dating back to 2007...
  • Having names like grnt instead of Grant was done by a single person who isn't active with PoC anymore. So there is work ongoing behind the scenes to release a drastically updated PoC Library with things like that cleaned up!
    Besides interface updates, it will bring this when finished:
    • New IO interfaces
    • A full AXI component set for AXI4, AXI4-Lite and AXI4-Stream
    • Additional OSVVM verification models
    • performance enhancements and less hardware resources
    • improved timing and constraints
    • an interface from AXI register descriptions to generate data structures for e.g. C
    • full traceability of Git repository state in a read-only register
  • For records vs. Vectors: That's a question what tools are supported. The current "public" version of PoC is compatible to ISE. An updated version will skip all this change interfaces.
  • For reuse, I haven't seen any IP core out there either as open source or commercial that has more reuse then PoC in itself.
    • Try to find a library where IP cores work the same way on Microsemi, Lattice, Intel and AMD FPGAs or can be synthesized to ASICs!
Brian Padalino
@bpadalino
@Paebbels understandable .. i like the lofty goal of PoC then .. it just seems like the internal consistency needs to be remedied, which seems you are trying to do
so kudos to that for sure .. other than that, i noticed the VHDL coding guidelines stated whitespace recommendations of 2 spaces which, personally, i don't like .. but i am curious if there are actual language based guidelines which should be used .. such as - when writing subprograms which take in std_logic_vector, always alias to a known vector index scheme ..
Patrick Lehmann
@Paebbels
Yes for sure. It was always hard fighting at university to bring components together.
And I'm willing to break interfaces to align naming. It might not be a naming style everyone will agree on, but it will be consistent!
we use one tab per indentation level (because that's what TABs are fore ...). we also add .editorconfig files to repositories.
Brian Padalino
@bpadalino
i think of other programming languages, and the fact there is a "standard library" that is commonly associated with it .. that people can pick up from to stand on the shoulders of giants .. i think it helps reduce the burden of entry and also shows as an example of how to write "good code"
i dunno, tabs are supposed to work that way but it never does, does it?
Patrick Lehmann
@Paebbels
PoC will also be split in two parts in the future. The PoC library will continue to hold IP cores, the helper packages will go into CoreLibrary. Besides this, PoC will kick out the simulation helpers and transition to OSVVM for IP core tests.
Brian Padalino
@bpadalino
what are the timelines for these things ?