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  • Feb 03 02:13

    umarcor on keep-compiling

    ci: use the built-in '--keep-co… (compare)

  • Feb 03 02:12

    umarcor on cosim

    cosim/dpi-ffi: add 'vhdpi_ghdl.… cosim/dpi-ffi: add VHDPI_Test (compare)

  • Feb 03 01:56

    umarcor on cosim

    WIP setenv (compare)

  • Feb 03 01:55

    umarcor on main

    cosim/dpi-ffi/ghdl-vffi/test: a… (compare)

  • Feb 03 01:54

    umarcor on cosim

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  • Feb 03 01:52

    umarcor on main

    WIP envvars (compare)

  • Feb 03 01:50

    umarcor on cosim

    WIP envvars (compare)

  • Feb 02 23:13

    umarcor on master

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  • Feb 02 23:13

    umarcor on main

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  • Feb 02 23:13

    umarcor on cosim

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  • Feb 02 23:10

    umarcor on master

    cosim/dpi-ffi: create subdir 'g… cosim/dpi-ffi: fix compilation … cosim/dpi-ffi/ghd-vffi: use VUn… and 2 more (compare)

  • Feb 02 22:58

    umarcor on cosim

    ci: add workflow CoSim cosim/dpi-ffi: add README (compare)

  • Feb 02 22:45

    umarcor on cosim

    ci: add workflow CoSim cosim/dpi-ffi: add README (compare)

  • Feb 02 22:43

    umarcor on cosim

    cosim/dpi-ffi: create subdir 'g… cosim/dpi-ffi: fix compilation … cosim/dpi-ffi/ghd-vffi: use VUn… and 2 more (compare)

  • Oct 05 2021 13:29

    umarcor on top-subtype

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  • Oct 05 2021 13:28

    umarcor on master

    2008: ad tb_top_generic_subtype cosim: add ref to aguinet/drago… (compare)

  • Sep 24 2021 20:07

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 24 2021 19:59

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 24 2021 19:54

    umarcor on top-subtype

    2008: ad tb_top_generic_subtype (compare)

  • Sep 23 2021 01:45

    umarcor on style

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Farmadupe
@Farmadupe
...I guess alternatively the spec could have not awkwardly borrowed the syntax for string literals for use with bit string literals
Nicolas Pinault
@NicoPy
All this makes sense.
The funny thing is that you can write signal Test : std_logic_vector (8-1 downto 0) := "00000000"; Here the string literal is automatically converted to bit_string literal.
But you can't write signal Test : std_logic_vector (8-1 downto 0) := "0000_0000";
Richard Head
@trickyhead_gitlab
not only is it converted to a "bit_string_literal" but actually interpreted as binary. so b"0000_0000" would be fine
Nicolas Pinault
@NicoPy
For me, there is some sort of inconsistency here.
Brian Padalino
@bpadalino
what's the inconsistency ?
Nicolas Pinault
@NicoPy
"00000000"which is a string is automatically converted to bit_string litteral. While "0000_0000" is not automatically converted.
Farmadupe
@Farmadupe
ah, I think it's implicit in the spec that if a literal is a bit_string_literal, it can never be type inferred to be a 'actual string'
an also, because the spec is using the langauge of teh grammar when describing unerline deletion, it's also inferred that type resolution will not have been done at the point of underline deletion
oh, so to reply to your last comment, "00000000" is never converted to bit string literal, as the spec says this conversion doesn't exist. It is type inferred to be a "bitty" type, no a "stringy" type
Nicolas Pinault
@NicoPy
Yes, this is a subtle difference (convertion / type inference) which has its consequences.
Jari Honkanen
@johonkanen
Why assignment operators := and <= are not overloadable? Could they be made overloadable?
2 replies
Farmadupe
@Farmadupe
as a guess 1) Either to avoid having to reword any sections of the Ada spec when drafting VHDL'87, or 2) to avoid the code author having to remember whether an identifier is a sig/var when reading code for the first time
1) is just a wild guess on my part though, 2) feels more plausible to me
Brian Padalino
@bpadalino
@johonkanen what's your use case for wanting to overload them ?
Farmadupe
@Farmadupe
(possibly flipflopping over whether to use a signal or a shared-variable?)
Brian Padalino
@bpadalino
you think he means to allow := to operate like <= and vice versa ?
i read it to mean he wants to be able to overload what := means for different types
so instead of assignment requiring the same type on both sides, one could overload := to take in integer and return a std_logic_vector
Jim Lewis
@JimLewis
@johonkanen they are not operators.
Farmadupe
@Farmadupe
ohh inteeresting, I guess that is what they'd said asked for, my head jumped to interchangeability
Jim Lewis
@JimLewis
If they were operators then what they currently do is allow like type to be assigned to like type.
If they were overloadable one could create conversions in the assignment operation.
Brian Padalino
@bpadalino
right .. but if you already have to write the conversion subprogram, being able to name it <= or := is just syntactic sugar, and possibly confusing
Jari Honkanen
@johonkanen
Mostly that would be useful syntactic sugar for assigning real valued constants directly to floating point objects instead of writing to_float(3.517) or equivalent for each. This is so common automatic conversion that practically every language does it.
Farmadupe
@Farmadupe
hmm how do other languages eachieve this without creating circular references? imagine.. function ":="(lhs : some_type; rhs : some_type) return some_type is begin lhs := rhs; end; <- creates an infinite recursive loop
Jari Honkanen
@johonkanen
Also, if we want to overload other operators like "+", "-" etc, then being able to overload the assigment operator would make the conversion call automatically, which is slighly more convenient than writing integer_signal <= to_integer(signed_a + signed_b). Though the effort here is so small that it is debatable whether clarity would be more valuable than very slight convenience.
Brian Padalino
@bpadalino
@Farmadupe what are you returning in that function? a call to itself? i don't think assignment operators are given both left and right sides .. just one and you return the other
it seems like @johonkanen is looking more for like an implicit conversion .. so he doesn't have to keep writing to_float
but i think that implicit conversion goes against the strong typing of vhdl/ada
sckoarn
@sckoarn
@JimLewis Please confirm you go my direct message ... we would like to contribute back our standards test cases.
2 replies
sckoarn
@sckoarn
@Paebbels looks like you are the one to contact regarding standards test suite ? Drop me a note or invite so we can start having a look at the process.
Jim Lewis
@JimLewis
Anyone know what www.thecodingforums.com is? Is it a safe site or are they mirroring other sites?
Farmadupe
@Farmadupe
Looking at the post count on some of the subforums it seems fairly dead. Seems unlikely that someone mirroring content for nefarious purposes would choose to mirror an almost empty webforum
Patrick Lehmann
@Paebbels

@Paebbels looks like you are the one to contact regarding standards test suite ? Drop me a note or invite so we can start having a look at the process.

What have I won?

sckoarn
@sckoarn
An all expense payed trip to Gnowere.
Jim Lewis
@JimLewis
@Farmadupe it looks like it has some conversations from comp.lang.vhdl. which would correlatate with low bandwidth
Brian Padalino
@bpadalino
this might be beating a dead horse a bit, but i was just made aware of these old VHDL-93 tests: https://github.com/nickg/vests/tree/master/vhdl-93/billowitch ... and i know there isn't something like this for VHDL-2008 and definitely nothing like this for VHDL-2019 .. what do you think it would take to describe tests for just the new stuff such that it could be used for some type of rudimentary testing? not comprehensive, but at least basic ?
Brian Padalino
@bpadalino
@umarcor i was reminded of this repository - https://github.com/VHDL/Compliance-Tests .. i saw the LCS2019.yml file here - https://github.com/VHDL/Compliance-Tests/blob/main/issues/LCS2019.yml .. is there something similar that can be taken from the twiki archive that @JimLewis has that could be used for vhdl-2008 as well?
@JimLewis do you have any contacts over at aldec that you could ask who may want to share how they do regression/compliance testing for their vhdl stuff?
Farmadupe
@Farmadupe
hmm out of interest, does anyone know where the 'v' in modelsim came from? Sorta guessing it's just 'v' for verilog/vhdl
Brian Padalino
@bpadalino
i think it's vhdl based since they use vcom for vhdl, and vlog for verilog
but sure, probably that
sckoarn
@sckoarn
Is there a place to talk about cross-language interfaces VHDL <-> Verilog?
Brian Padalino
@bpadalino
there was an open vhdl wg ticket i thought .. let me see if i can find it
sckoarn
@sckoarn
I would be more than happy to work on a standard for this
Brian Padalino
@bpadalino
oh, sorry - this was regarding VHPI/DPI/FFI .. unsure if this counts as that, or you meant something higher level - https://umarcor.github.io/ghdl-cosim/vhdl202x/index.html and IEEE-P1076/VHDL-Issues#10 i think try to capture the former
sckoarn
@sckoarn
That is DPI.
Brian Padalino
@bpadalino
then i haven't found anything specific regarding SV cosimulation or anything ..
sckoarn
@sckoarn
It is kind of known that there is no standard.
Brian Padalino
@bpadalino
though i did have an idea over the weekend to use VHPI/DPI and use open source simulators to cosimulate