2 replies
this might be beating a dead horse a bit, but i was just made aware of these old VHDL-93 tests: https://github.com/nickg/vests/tree/master/vhdl-93/billowitch ... and i know there isn't something like this for VHDL-2008 and definitely nothing like this for VHDL-2019 .. what do you think it would take to describe tests for just the new stuff such that it could be used for some type of rudimentary testing? not comprehensive, but at least basic ?
@umarcor i was reminded of this repository - https://github.com/VHDL/Compliance-Tests .. i saw the LCS2019.yml file here - https://github.com/VHDL/Compliance-Tests/blob/main/issues/LCS2019.yml .. is there something similar that can be taken from the twiki archive that @JimLewis has that could be used for vhdl-2008 as well?
@JimLewis do you have any contacts over at aldec that you could ask who may want to share how they do regression/compliance testing for their vhdl stuff?
but sure, probably that
oh, sorry - this was regarding VHPI/DPI/FFI .. unsure if this counts as that, or you meant something higher level - https://umarcor.github.io/ghdl-cosim/vhdl202x/index.html and IEEE-P1076/VHDL-Issues#10 i think try to capture the former
as a proof of concept
Well it seems that \DuT#% is the Verilog derivative ... so my VHDL lib has one name and Verilog has another? How can they ever match?
going further \Dut wSpace\ ID with a space in it. Verilog will terminate at the space?
So the rule I would make is that "extended" identifiers may not be used in cross language interfaces. End of story.
As in using the name in an interface which is a keyword in the other language?
Though it is a problem there is no group trying to fix it, is there?
SV will never do it.