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  • Apr 02 2017 21:44
  • Mar 29 2017 21:43

    lievenlemiengre on views

    Validated & fixed definitions w… (compare)

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    Paebbels on views

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  • Mar 29 2017 20:49

    Paebbels on views

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    Paebbels on views

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    Paebbels on views

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  • Mar 07 2017 02:41

    Paebbels on range-arithmetic

    Added range arithmetic packages… (compare)

  • Mar 07 2017 02:23

    Paebbels on generic-list

    Committed pending changes. (compare)

  • Dec 27 2016 11:05

    tmeissner on tbv2_associative_array

    Add tests for dict with strings… (compare)

  • Dec 11 2016 16:37

    LarsAsplund on tbv7-event-object

    Added more test cases (compare)

  • Dec 11 2016 16:33

    LarsAsplund on tbv7-event-object

    Cleaning up Added more test cases (compare)

  • Oct 04 2016 18:42

    tmeissner on tbv2_associative_array

    Some fixes to make generic dict… (compare)

  • Sep 26 2016 20:07

    Paebbels on master

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  • Sep 22 2016 19:23

    Paebbels on math

    Based math test cases on Python… Made stimuli generation adapt t… Merge pull request #3 from Lars… (compare)

  • Sep 22 2016 19:23
    Paebbels closed #3
  • Sep 22 2016 19:23
    Paebbels commented #3
  • Sep 21 2016 22:32
    cmarqu commented #2
  • Sep 21 2016 20:44
    Paebbels commented #2
  • Sep 21 2016 20:40
    LarsAsplund commented on 10eb07b
  • Sep 21 2016 20:30
    LarsAsplund synchronize #3
T. Meissner
@tmeissner
We all are lazy. But sometimes the lazyness isn't supported by the tools ;)
Patrick Lehmann
@Paebbels
PREC_A is not a power of 2.
FranzForstmayr
@FranzForstmayr
So vivado can't just upscale to let's say 64 bits?
Patrick Lehmann
@Paebbels
Thus the record is not a power of two, thus the array indices do not address at boundaries of power of two numbers, thus no multiplexer can be used to address your array
it's not vivado, it's the language, it's statically typed, there is no upscaling
Igmar Palsenberg
@igmar
You get what you ask for usually
Patrick Lehmann
@Paebbels
if you go to an ASIC, you don't want upscaling, you want what you describe :)
so you need two conversion functions, that convert your user descific unalignable datatype to power of two sizes
FranzForstmayr
@FranzForstmayr
That's a point. So adding dummy zeros should work in this case
Patrick Lehmann
@Paebbels
then you can describe your memory as usual and you don't need a BRAM primitive as suggested by @tmeissner
FranzForstmayr
@FranzForstmayr
Would it be possible, if PREC_A is set to let's say 16?
Patrick Lehmann
@Paebbels
then it should be possible
if it now fails, then it's the missing cleverness of Vivado :)
I tried to write it in a positive way
FranzForstmayr
@FranzForstmayr
Haha :D
But LUT primitives wouldn't be as efficient as BRAM instances i think?
Wouldn't i need a LUT per bit?
FranzForstmayr
@FranzForstmayr
Still the same
WARNING: [Synth 8-5858] RAM bram_cont_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
eine
@eine

I am not sure about the point being that the size of the record is not a power of two. I'd say that I have inferred memories of say 1024 elements of 13 bits. Vivado was able to infer a BRAM of 1024x13 (actually, , 2K x 18, which is the closest). So, it might work just by converting the record elements to a std_logic_vector:

bram_mem(addr) <= complex.Re & complex.Im;

and

if rising_edge(clk) then
  outstd <= bram_mem(addr);
end if;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

Note that you don't need any function. Just a concurrent assignment for each element in the record.
If Vivado does still not get the pattern, you might need to add another signal for the writing part:

instd <= complex.Re & complex.Im;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

if rising_edge(clk) then
   bram_mem(addr) <= instd;
end if;
if rising_edge(clk) then
   outstd <= bram_mem(addr);
end if;
NBilginN
@NBilginN
hi
eine
@eine
Hi!
NBilginN
@NBilginN
I am learning vhdl and I was searching a vhdl chat room and I found here. Are all of you students?
eine
@eine
There's many different people here. Some are undergraduate students, others PhD candidates; but I'd say that most are engineers that either do hardware design in VHDL, develop open source tools/frameworks in VHDL and/or are involved in teaching VHDL.
As explained in http://www.vhdl.net/, I think that this chat room was created as the Open Source section of http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome
Nonetheless, feel free to ask. Even though this is not a 'VHDL learning group', we can probably help you find open source resource for you to learn.
Andre Souto
@suoto

Hi all, hopefully it's OK to ask this here :)

Does anyone has an idea on how well are VHDL records supported on non FPGA related tools (things like Synopsys, commercial linters, formal tools, etc)? Or more broadly, are there guidelines or manuals for these tools outlining what constructs are actually supported?

To give a little context to the question, my current company develops an IP which can target either FPGAs or ASICs and because we don't know what constructs are actually supported, we have to be very conservative; this imho is holding us back a bit. Records for example could help quite a bit in making it easier to understand some parts for example.

Patrick Lehmann
@Paebbels
If a tool doesn't support records, you should call this a tool supporting VHDL, because records are a very basic feature. I have never seen a tool not supporting records. (unconstrained records is a different question...)
Smplify Pro has very good VHDL support, even supportig VHDL-2008 in synthesis.
Andre Souto
@suoto
That's my gut feeling as well wrt records, same with unconstrained. There's a general fear of some tool not supporting, which imo is a problem of whoever chose to use it in the first place
Patrick Lehmann
@Paebbels
The PoC Library has techniques to figure out if a tool supports such features.
One needs to implement a class in Python for the tool and then this tool can be used to test the compatibility
Andre Souto
@suoto
Has the LEON3 been implemented on ASIC as well? That'd be a good starting point
Problem is wrt to Synplify for example is we don't have licences, otherwise it would be much easier to determine what works and what doesn't work
Patrick Lehmann
@Paebbels
I think LEON3 alsoalso ASIC tested.
what tools are you using?
Andre Souto
@suoto
I haven't been involved too much in this project, seems to be Synopsys Design Compiler
Patrick Lehmann
@Paebbels
you could try to compile components from PoC Library
if it survives this, then the tool is good :)
Andre Souto
@suoto
Yeah, only need a Synopsys license :-\
I mean, to me it sounds very weird trying to support ASIC without having tools to do it right
tgingold
@tgingold
Yes, there are many implementations of Leon3 in ASIC, in particular the rad-harden ones.
Lars Asplund
@LarsAsplund
While Vivado supports records I vaguely remember it was not recommended not long ago. I don't think I ever had any problems though.
Lars Asplund
@LarsAsplund
Just started on a small design for Lattice the other day. Yesterday it started to pass my tests so today it's time to start synthesizing. I haven't used Lattice or Synplify for over a decade so I have no idea what to expect when crunching my VHDL-2008 infested designs. It will be interesting.
T. Meissner
@tmeissner
In my experience Synplify is quite good in supporting VHDL-2008.
I only remember one thing. I had to unroll a multiplexer with variable slices to a case/if construct some time ago, but that wasn’t a VHDL-2008 thing.
Andre Souto
@suoto
Cool, really appreciate the responses
Andre Souto
@suoto
Do formal equivalence/verification tools like FormalPro support records (and more modern vhdl stuff) as well?
T. Meissner
@tmeissner
I only know Mentors formal tools (and Symbiyosys). The VHDL code never had to be changed to process it with mentors propcheck or SymbioticEDAs Symbiyosys
I’ve only done property checking, no equivalence checking
Sometimes you have to change your PSL/SVA properties, as formal tools often don’t support the full richness of these languages
Colin Marquardt
@cmarqu
Now that the VHDL-2019 standard is out, is the Framemaker document being exported in as many formats as possible so that hopefully all semantic information stays available (maybe by merging of information from several formats)?