VHDL/Lobby

I am not sure about the point being that the size of the record is not a power of two. I'd say that I have inferred memories of say 1024 elements of 13 bits. Vivado was able to infer a BRAM of 1024x13 (actually, , 2K x 18, which is the closest). So, it might work just by converting the record elements to a std_logic_vector:

bram_mem(addr) <= complex.Re & complex.Im;

and

if rising_edge(clk) then
  outstd <= bram_mem(addr);
end if;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

Note that you don't need any function. Just a concurrent assignment for each element in the record.
If Vivado does still not get the pattern, you might need to add another signal for the writing part:

instd <= complex.Re & complex.Im;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

if rising_edge(clk) then
   bram_mem(addr) <= instd;
end if;
if rising_edge(clk) then
   outstd <= bram_mem(addr);
end if;