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  • Feb 11 22:48
    tmeissner commented #4
  • Feb 03 18:51
    tmeissner commented #4
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  • Feb 03 18:35
    Paebbels labeled #4
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  • Feb 03 17:48
    JimLewis opened #4
  • Apr 02 2017 21:44
  • Mar 29 2017 21:43

    lievenlemiengre on views

    Validated & fixed definitions w… (compare)

  • Mar 29 2017 21:16

    Paebbels on views

    Added view implementations for … (compare)

  • Mar 29 2017 20:49

    Paebbels on views

    Added a view implementation for… (compare)

  • Mar 29 2017 20:38

    Paebbels on views

    Renamed package files to `*.pkg… (compare)

  • Mar 29 2017 20:34

    Paebbels on views

    Added first implementation of l… (compare)

  • Mar 07 2017 02:41

    Paebbels on range-arithmetic

    Added range arithmetic packages… (compare)

  • Mar 07 2017 02:23

    Paebbels on generic-list

    Committed pending changes. (compare)

  • Dec 27 2016 11:05

    tmeissner on tbv2_associative_array

    Add tests for dict with strings… (compare)

  • Dec 11 2016 16:37

    LarsAsplund on tbv7-event-object

    Added more test cases (compare)

  • Dec 11 2016 16:33

    LarsAsplund on tbv7-event-object

    Cleaning up Added more test cases (compare)

  • Oct 04 2016 18:42

    tmeissner on tbv2_associative_array

    Some fixes to make generic dict… (compare)

  • Sep 26 2016 20:07

    Paebbels on master

    Updated URL (compare)

svenn71
@svenn71
is q <= '0' when reset else d if rising_edge(clock); allowed in vhdl-2008?
T. Meissner
@tmeissner
I have used similar constructs, but in different order of reset & clock.
But I don’t know if it’s LRM compliant
eine
@eine
I would say that is an LRM compliant register with async reset.
Not sure about synthesis tools understanding it, tho.
Patrick Lehmann
@Paebbels

in verilog it is possible to do sig <= {8'd9, 8'h5} is there something equal in vhdl?

It is:
sig <= 8d"9" & 8x"5"

These are bitstring literals with modifiers:

  • x => hex
  • o => octal
  • d => decimal
  • b => binary

The number in front of the modifier is the length in bits to generate.

The modifier can be specified as signed or unsigned with s and u
E.g. 8ux"5"
This is important if bit sizes are more or less the the given number and the sign bit needs to be extended or reduced.

is q <= '0' when reset else d if rising_edge(clock); allowed in vhdl-2008?

if is not allowed in this, you need a second when.
See in PoC's components package for different one-liner flip-flops.

q <= ffdre(Q => q, D => data, => RST => Reset) when rising_edge(Clock);
enable and INIT is optional
eine
@eine
Patrick, what about q <= '0' when reset else d when rising_edge(clock); ?
Patrick Lehmann
@Paebbels
I'm unsure if synthesizers will understand this and/or when reset becomes async :)
svenn71
@svenn71
I am strugling to find documentation on the difference between x"" and X"" in my google searches
But I know how important it is to avoid 'X' in simulation :)
Jim Lewis
@JimLewis
@eine you should report it as a bug. That code is supported by 1076.6-2004. Annoying vendors dont support this
Aaron Panella
@a-panella
hey all, was wondering if anyone has any insight re: data structures to use for large amounts of data. Would it be ill-advised to attempt to simulate an array of length 16384, containing 28 bit elements? I am running into some trouble with .ghw files when I try to do this. Should I perhaps use OSVVM data types instead?
Richard Head
@trickyhead_gitlab
@a-panella 16kx28 unlikely to be much of an issue. For example, Xilinx BRAMs are 1k x 18 bits, and a UUT could have many of these and its not an issue tooday. For large rams (like DDR), it can be useful to model them as sparse memories, and several ways to do this can be acheived.
trying to monitor on a waveform might be problematic though
Aaron Panella
@a-panella
@trickyhead_gitlab thanks for the insight. Im finding ghdl can simulate it fine, but when it is buried down several layers of hierarchy, the ghw just hangs gtkwave
Lars Asplund
@LarsAsplund
@a-panella Where is the ghw format defined?
Aaron Panella
@a-panella
Thats a good question, I couldnt find a proper reference to it months ago when i looked
Unai Martinez-Corral
@umarcor
1-2 weeks ago I modified GHDL's makefiles so that libghw is built and installed by default now. I need to update that in the article.
Aaron Panella
@a-panella
Thanks @umarcor havent used libghw but have used ghwdump to check for ghw errors
Ben Reynwar
@benreynwar
Are there any VHDL-19 to universally-supported-VHDL converters around? I was checking out the IEEE-P1076 gitlab and trying to think of where VHDL was limiting, but realized that most of the features I would like in synthesizable VHDL are already there, they're just not supported.
Richard Head
@trickyhead_gitlab
@benreynwar Ive not seen one for any version. The only ones I saw were David Bishops 1993 versions of the 2008 libraries
Unai Martinez-Corral
@umarcor
@benreynwar, the only similar solution I know is GHDL's synth command. However, GHDL does not support VHDL 2019 features yet.
As a community, I believe we need a solution for boosting the development of GHDL.
Ben Reynwar
@benreynwar
@umarcor OK, thanks. Using ghdl synth for this is a really interesting idea.
Aaron Panella
@a-panella
general question around synthesis tools: is it generally okay to do something like this: result <= a + b + c when you know your DSP slice implementations take 2 operands? I'm getting some pretty magical results on chip for assignments that are behaving nicely in simulation...
would that thought it is okay and the tools will cascade DSPs if they need to, but the results I am getting are pretty random looking considering I don't have timing or CDC issues...
Richard Head
@trickyhead_gitlab
@a-panella Synth tools are normally very good at optimising the netlist. But can sometimes throw up anomalies. Im of the opinion that you should code it easily readable first and fix it later if there is a problem. Ive seen plenty of "optimised" code re-written and thrown away over the years because people were chasing the chip rather than thinking about future readability.
Jim Lewis
@JimLewis

First I agree 100% with @trickyhead_gitlab WRT readability being # 1 concern - that drives reuse.

Just consider, if you receive an entity from one of your colleagues, are you going to reuse it you cannot read what they did or are you going to write your own?

Next what I have been seeing in synthesis is that Y <= A + B is implemented in regular LUTs. In addition, I am seeing more implementations supporting Carry Sum/Save Adders in LUTs. Meaning that one LUT can implement one bit of Y <= A + B + C ; in a good synthesis tool and target implementation

Aaron Panella
@a-panella
Thanks @trickyhead_gitlab @JimLewis for the advice
re: using HDL that is hard to understand - I tend to write my own as I find HDL a hard subset of languages to read and understand properly especially when you have monolithic files. I'll have to think of something to debug this weird behaviour then...
Aaron Panella
@a-panella
secondary question @trickyhead_gitlab @JimLewis perhaps my issues are coming from using the numeric_std function to_integer in my design.. Is this something that should generally be avoided? I can see that an undefined bitwidth could probably cause some strange issues depending on the synthesiser, but I assumed that vivado would default to a reasonble number such as 32
Richard Head
@trickyhead_gitlab
@a-panella The "default" in vivado is 32 bits (signed) for integers, bit it is also good at removing unnecessary logic. For example, if you have this, Vivado, will keep temp only as 9 bit, as that is all that is required:
op : out unsigned(8 downto 0);

signal a,b : unsigned(7 downto 0);
signal temp : integer;


process(clk)
begin
  if rising_edge(clk) then
    temp <= to_integer(a)+ to_integer(b);
    op <= to_unsigned(temp, op'length)
  end if;
end process;
Jim Lewis
@JimLewis
@a-panella Generally I am doing my math using types unsigned, signed, ufixed, sfixed. Are you using type integer? Yes. Integers can be 32 bits of signed values or 31 bits unsigned. Integers don't get bigger than that. I have never had an issue with to_integer - yet I have never used it for math (to_integer).
Aaron Panella
@a-panella
hmmm, interesting, thanks
Richard Head
@trickyhead_gitlab
The Key is understanding what circuit you are trying to describe before writing it, and then checking that what vivado did matches. This can be very useful when having to pipeline items later when they dont meet timing, as you have to re-imagine the circuit in the problem area, and understanding what knock-on effects of your pipelining is.
Aaron Panella
@a-panella
yep, I have a decent understanding of how my HDL should synthesise on the chip, just occaisonally getting weird behaviour. Going to check my CDCs as thats really the only thing that makes sense to be broken and cause these results
Jim Lewis
@JimLewis
Is the issue only after powerup or is it also happening during run time? If only after powerup you need to check that your reset circuits deassert synchronously.
Aaron Panella
@a-panella
it happens not on powerup but at runtime (but not all the time) I suspect it is a bus cdc sync issue, i've added proper handshake in and will be running a build later to see if that is causing the issue. I was ILA sampling the operands in the incorrect clk domain as well, so it may have appeared that the inputs were fine when they were not... plenty of things to check now :)
Aaron Panella
@a-panella
hey all, quick question on packages and entity component (maybe?) declaration and instantiation in them
I'm trying to use a cdc design that mocks one of Xilinx's xpm_cdcs. So my synthesisable VHDL has a statement like this: use xpm.vcomponents.all in order to synthesise the xpm_cdc. However, the mock cdc that I have for simulation with GHDL (vhdl only, hence no verilog libs such as xilinx xpm). In simulation, I can use the mock, but the mock entity is not declared in any packages. so my question is, can I just wrap the entity in a package? what does the syntax for this look like? I was thinking something like this:
Aaron Panella
@a-panella
package vcomponents is 
  entity xpm_cdc is port( ...); end entity xpm_cdc;
end package vcomponents;
package body vcomponents is
  architecture rtl of xpm_cdc is 
     begin
     --implementation details
   end rtl;
end package body vcomponents;
I suppose the entity would be a component instead, but is this possible?
or can you only declare in a package?
Patrick Lehmann
@Paebbels
You put a component with same interface and name as the XPM into a package with the same name as Xilinx uses.
Aaron Panella
@a-panella
Thanks patrick!