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  • Apr 02 2017 21:44
  • Mar 29 2017 21:43

    lievenlemiengre on views

    Validated & fixed definitions w… (compare)

  • Mar 29 2017 21:16

    Paebbels on views

    Added view implementations for … (compare)

  • Mar 29 2017 20:49

    Paebbels on views

    Added a view implementation for… (compare)

  • Mar 29 2017 20:38

    Paebbels on views

    Renamed package files to `*.pkg… (compare)

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    Paebbels on views

    Added first implementation of l… (compare)

  • Mar 07 2017 02:41

    Paebbels on range-arithmetic

    Added range arithmetic packages… (compare)

  • Mar 07 2017 02:23

    Paebbels on generic-list

    Committed pending changes. (compare)

  • Dec 27 2016 11:05

    tmeissner on tbv2_associative_array

    Add tests for dict with strings… (compare)

  • Dec 11 2016 16:37

    LarsAsplund on tbv7-event-object

    Added more test cases (compare)

  • Dec 11 2016 16:33

    LarsAsplund on tbv7-event-object

    Cleaning up Added more test cases (compare)

  • Oct 04 2016 18:42

    tmeissner on tbv2_associative_array

    Some fixes to make generic dict… (compare)

  • Sep 26 2016 20:07

    Paebbels on master

    Updated URL (compare)

  • Sep 22 2016 19:23

    Paebbels on math

    Based math test cases on Python… Made stimuli generation adapt t… Merge pull request #3 from Lars… (compare)

  • Sep 22 2016 19:23
    Paebbels closed #3
  • Sep 22 2016 19:23
    Paebbels commented #3
  • Sep 21 2016 22:32
    cmarqu commented #2
  • Sep 21 2016 20:44
    Paebbels commented #2
  • Sep 21 2016 20:40
    LarsAsplund commented on 10eb07b
  • Sep 21 2016 20:30
    LarsAsplund synchronize #3
Josh
@joshrsmith
just not as a top level IP file?
Patrick Lehmann
@Paebbels
it's one of Xilinx's tries to disrepute VHDL / VHDL-2008
any VHDL file in your IP core can be VHDL-2008
I don't use VHDL 93 anymore
Jevin Sweval
@jevinskie
Relationships with EDA vendors are almost always abusive. What “fun”. =\
FranzForstmayr
@FranzForstmayr
I'm often getting this warning from vivado
WARNING: [Synth 8-5858] RAM bram_cont_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
Is vivado really too dumb, to map a record into a vector for using in a bram, or is there another reason behind?
Patrick Lehmann
@Paebbels
Please show the datatype definition.
FranzForstmayr
@FranzForstmayr
constant PREC_A : integer := 27;
subtype signed_prec_a_t is signed(PREC_A - 1 downto 0);
type complexs_a_t is record
    Re : signed_prec_a_t;
    Im : signed_prec_a_t;
end record;
type complexs_a_arr_t is array(natural range <>) of complexs_a_t;
signal bram_mem: complexs_a_arr_t(LEN - 1 downto 0);
T. Meissner
@tmeissner
Is there any synthesis tool that map this to a bram? How should the tool know which vector representation you want?
FranzForstmayr
@FranzForstmayr
I want to access one complexs_a_t by address, so i simply write in my process:
blabla
if rising_edge(clk) then
    outsig <= bram_mem(addr)
end if;
So it's obvious, that one memory cell should carry a complexs_a_t.
T. Meissner
@tmeissner
I mean the record. There is no array representation of a record. You have to do that by yourself I think.
FranzForstmayr
@FranzForstmayr
Isn't signed a array representation itself? I mean i don't care about LSB, MSB first or Re, Im first in that case. It's just a 54 bit sequence.
T. Meissner
@tmeissner
Do you want a BRAM instance or only to synthesize it to registers?
FranzForstmayr
@FranzForstmayr
A BRAM instance. It is actually a register memory, but it's too big in my case.
T. Meissner
@tmeissner
In the first case I assume that the synthesis tool cannot convert the record to an array. I think you have todo it by yourself, But I'm not sure
you also cannot do array <= record; in vhdl
there is no implicit conversion for that I think
FranzForstmayr
@FranzForstmayr
I can write a function for this case, of course. But this is somewhat essential, so i thought the tools can do this for me. Would be the same, if you would manually define the bit locations in a C structure.
I don't want to work as a human compiler :D
T. Meissner
@tmeissner
It looks like more of a problem with automatic BRAM instantiation. The synthesis tool seems to be able to map it to registers, but not to BRAM instances. Sometimes these tools are not so clever, so you have to use specific patterns to get the bram recognized. Like in the old days when there were specific patterns to get registers, adders or other stuff.
Better be specific to get the results you need ;)
T. Meissner
@tmeissner
But maybe @Paebbels can you help better, he has a much better knowledge of the language than I have ;)
FranzForstmayr
@FranzForstmayr
I'm too young to know the old dates :D. But you're probably right, it's just exactly this problems prevents you from efficient coding. In my case I'll need about 40 simultaneous read/write operations, so 20 BRAMs would be needed. You cannot put them altogether in a process with an variable mem, otherwise vivado isn't detecting them. So make a generate loop around the processes and put each BRAM into one process. At this moment, i cannot use my RW interface port any more, because it would require multiple write access to a single signal. So you need blocks, define signals in there and write to the read port concurrently. Sometimes, some memory is just pain
T. Meissner
@tmeissner
I always instantiate BRAM explicitly, so I don't run in such problems ;)
FranzForstmayr
@FranzForstmayr
I'm a lazy guy :)
T. Meissner
@tmeissner
We all are lazy. But sometimes the lazyness isn't supported by the tools ;)
Patrick Lehmann
@Paebbels
PREC_A is not a power of 2.
FranzForstmayr
@FranzForstmayr
So vivado can't just upscale to let's say 64 bits?
Patrick Lehmann
@Paebbels
Thus the record is not a power of two, thus the array indices do not address at boundaries of power of two numbers, thus no multiplexer can be used to address your array
it's not vivado, it's the language, it's statically typed, there is no upscaling
Igmar Palsenberg
@igmar
You get what you ask for usually
Patrick Lehmann
@Paebbels
if you go to an ASIC, you don't want upscaling, you want what you describe :)
so you need two conversion functions, that convert your user descific unalignable datatype to power of two sizes
FranzForstmayr
@FranzForstmayr
That's a point. So adding dummy zeros should work in this case
Patrick Lehmann
@Paebbels
then you can describe your memory as usual and you don't need a BRAM primitive as suggested by @tmeissner
FranzForstmayr
@FranzForstmayr
Would it be possible, if PREC_A is set to let's say 16?
Patrick Lehmann
@Paebbels
then it should be possible
if it now fails, then it's the missing cleverness of Vivado :)
I tried to write it in a positive way
FranzForstmayr
@FranzForstmayr
Haha :D
But LUT primitives wouldn't be as efficient as BRAM instances i think?
Wouldn't i need a LUT per bit?
FranzForstmayr
@FranzForstmayr
Still the same
WARNING: [Synth 8-5858] RAM bram_cont_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
1138-4EB
@1138-4EB

I am not sure about the point being that the size of the record is not a power of two. I'd say that I have inferred memories of say 1024 elements of 13 bits. Vivado was able to infer a BRAM of 1024x13 (actually, , 2K x 18, which is the closest). So, it might work just by converting the record elements to a std_logic_vector:

bram_mem(addr) <= complex.Re & complex.Im;

and

if rising_edge(clk) then
  outstd <= bram_mem(addr);
end if;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

Note that you don't need any function. Just a concurrent assignment for each element in the record.
If Vivado does still not get the pattern, you might need to add another signal for the writing part:

instd <= complex.Re & complex.Im;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)

if rising_edge(clk) then
   bram_mem(addr) <= instd;
end if;
if rising_edge(clk) then
   outstd <= bram_mem(addr);
end if;
NBilginN
@NBilginN
hi
1138-4EB
@1138-4EB
Hi!
NBilginN
@NBilginN
I am learning vhdl and I was searching a vhdl chat room and I found here. Are all of you students?
1138-4EB
@1138-4EB
There's many different people here. Some are undergraduate students, others PhD candidates; but I'd say that most are engineers that either do hardware design in VHDL, develop open source tools/frameworks in VHDL and/or are involved in teaching VHDL.
As explained in http://www.vhdl.net/, I think that this chat room was created as the Open Source section of http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome
Nonetheless, feel free to ask. Even though this is not a 'VHDL learning group', we can probably help you find open source resource for you to learn.