any VHDL file in your IP core can be VHDL-2008
I don't use VHDL 93 anymore
I'm often getting this warning from vivado
Is vivado really too dumb, to map a record into a vector for using in a bram, or is there another reason behind?
WARNING: [Synth 8-5858] RAM bram_cont_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registersIs vivado really too dumb, to map a record into a vector for using in a bram, or is there another reason behind?
constant PREC_A : integer := 27;
subtype signed_prec_a_t is signed(PREC_A - 1 downto 0);
type complexs_a_t is record
Re : signed_prec_a_t;
Im : signed_prec_a_t;
end record;
type complexs_a_arr_t is array(natural range <>) of complexs_a_t;
signal bram_mem: complexs_a_arr_t(LEN - 1 downto 0);
So it's obvious, that one memory cell should carry a complexs_a_t.
you also cannot do array <= record; in vhdl
there is no implicit conversion for that I think
I don't want to work as a human compiler :D
It looks like more of a problem with automatic BRAM instantiation. The synthesis tool seems to be able to map it to registers, but not to BRAM instances. Sometimes these tools are not so clever, so you have to use specific patterns to get the bram recognized. Like in the old days when there were specific patterns to get registers, adders or other stuff.
Better be specific to get the results you need ;)
I'm too young to know the old dates :D. But you're probably right, it's just exactly this problems prevents you from efficient coding. In my case I'll need about 40 simultaneous read/write operations, so 20 BRAMs would be needed. You cannot put them altogether in a process with an variable mem, otherwise vivado isn't detecting them. So make a generate loop around the processes and put each BRAM into one process. At this moment, i cannot use my RW interface port any more, because it would require multiple write access to a single signal. So you need blocks, define signals in there and write to the read port concurrently. Sometimes, some memory is just pain
it's not vivado, it's the language, it's statically typed, there is no upscaling
so you need two conversion functions, that convert your user descific unalignable datatype to power of two sizes
if it now fails, then it's the missing cleverness of Vivado :)
I tried to write it in a positive way
But LUT primitives wouldn't be as efficient as BRAM instances i think?
Wouldn't i need a LUT per bit?
Wouldn't i need a LUT per bit?
I am not sure about the point being that the size of the record is not a power of two. I'd say that I have inferred memories of say 1024 elements of 13 bits. Vivado was able to infer a BRAM of 1024x13 (actually, , 2K x 18, which is the closest). So, it might work just by converting the record elements to a std_logic_vector:
bram_mem(addr) <= complex.Re & complex.Im;and
if rising_edge(clk) then
outstd <= bram_mem(addr);
end if;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)Note that you don't need any function. Just a concurrent assignment for each element in the record.
If Vivado does still not get the pattern, you might need to add another signal for the writing part:
instd <= complex.Re & complex.Im;
outsig.Re <= outstd(outstd'left downto (outstd'left/2)+1);
outsig.Im <= outstd(outstd'left/2 downto 0)
if rising_edge(clk) then
bram_mem(addr) <= instd;
end if;
if rising_edge(clk) then
outstd <= bram_mem(addr);
end if;
As explained in http://www.vhdl.net/, I think that this chat room was created as the Open Source section of http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome
Nonetheless, feel free to ask. Even though this is not a 'VHDL learning group', we can probably help you find open source resource for you to learn.