But I don’t know if it’s LRM compliant
Not sure about synthesis tools understanding it, tho.
in verilog it is possible to do sig <= {8'd9, 8'h5} is there something equal in vhdl?
It is:sig <= 8d"9" & 8x"5"
These are bitstring literals with modifiers:
- x => hex
- o => octal
- d => decimal
- b => binary
The number in front of the modifier is the length in bits to generate.
The modifier can be specified as signed or unsigned with s and u
E.g. 8ux"5"
This is important if bit sizes are more or less the the given number and the sign bit needs to be extended or reduced.
is q <= '0' when reset else d if rising_edge(clock); allowed in vhdl-2008?
if is not allowed in this, you need a second when.
See in PoC's components package for different one-liner flip-flops.
q <= ffdre(Q => q, D => data, => RST => Reset) when rising_edge(Clock);
But I know how important it is to avoid 'X' in simulation :)
hey all, was wondering if anyone has any insight re: data structures to use for large amounts of data. Would it be ill-advised to attempt to simulate an array of length 16384, containing 28 bit elements? I am running into some trouble with .ghw files when I try to do this. Should I perhaps use OSVVM data types instead?
@a-panella 16kx28 unlikely to be much of an issue. For example, Xilinx BRAMs are 1k x 18 bits, and a UUT could have many of these and its not an issue tooday. For large rams (like DDR), it can be useful to model them as sparse memories, and several ways to do this can be acheived.
trying to monitor on a waveform might be problematic though
1-2 weeks ago I modified GHDL's makefiles so that
libghw is built and installed by default now. I need to update that in the article.
Are there any VHDL-19 to universally-supported-VHDL converters around? I was checking out the IEEE-P1076 gitlab and trying to think of where VHDL was limiting, but realized that most of the features I would like in synthesizable VHDL are already there, they're just not supported.
As a community, I believe we need a solution for boosting the development of GHDL.
general question around synthesis tools: is it generally okay to do something like this: result <= a + b + c when you know your DSP slice implementations take 2 operands? I'm getting some pretty magical results on chip for assignments that are behaving nicely in simulation...
would that thought it is okay and the tools will cascade DSPs if they need to, but the results I am getting are pretty random looking considering I don't have timing or CDC issues...
@a-panella Synth tools are normally very good at optimising the netlist. But can sometimes throw up anomalies. Im of the opinion that you should code it easily readable first and fix it later if there is a problem. Ive seen plenty of "optimised" code re-written and thrown away over the years because people were chasing the chip rather than thinking about future readability.
First I agree 100% with @trickyhead_gitlab WRT readability being # 1 concern - that drives reuse.
Just consider, if you receive an entity from one of your colleagues, are you going to reuse it you cannot read what they did or are you going to write your own?
Next what I have been seeing in synthesis is that Y <= A + B is implemented in regular LUTs. In addition, I am seeing more implementations supporting Carry Sum/Save Adders in LUTs. Meaning that one LUT can implement one bit of Y <= A + B + C ; in a good synthesis tool and target implementation
re: using HDL that is hard to understand - I tend to write my own as I find HDL a hard subset of languages to read and understand properly especially when you have monolithic files. I'll have to think of something to debug this weird behaviour then...
secondary question @trickyhead_gitlab @JimLewis perhaps my issues are coming from using the numeric_std function to_integer in my design.. Is this something that should generally be avoided? I can see that an undefined bitwidth could probably cause some strange issues depending on the synthesiser, but I assumed that vivado would default to a reasonble number such as 32
@a-panella The "default" in vivado is 32 bits (signed) for integers, bit it is also good at removing unnecessary logic. For example, if you have this, Vivado, will keep
temp only as 9 bit, as that is all that is required:op : out unsigned(8 downto 0);
signal a,b : unsigned(7 downto 0);
signal temp : integer;
process(clk)
begin
if rising_edge(clk) then
temp <= to_integer(a)+ to_integer(b);
op <= to_unsigned(temp, op'length)
end if;
end process;
@a-panella Generally I am doing my math using types unsigned, signed, ufixed, sfixed. Are you using type integer? Yes. Integers can be 32 bits of signed values or 31 bits unsigned. Integers don't get bigger than that. I have never had an issue with to_integer - yet I have never used it for math (to_integer).
The Key is understanding what circuit you are trying to describe before writing it, and then checking that what vivado did matches. This can be very useful when having to pipeline items later when they dont meet timing, as you have to re-imagine the circuit in the problem area, and understanding what knock-on effects of your pipelining is.
it happens not on powerup but at runtime (but not all the time) I suspect it is a bus cdc sync issue, i've added proper handshake in and will be running a build later to see if that is causing the issue. I was ILA sampling the operands in the incorrect clk domain as well, so it may have appeared that the inputs were fine when they were not... plenty of things to check now :)
I'm trying to use a cdc design that mocks one of Xilinx's xpm_cdcs. So my synthesisable VHDL has a statement like this: use xpm.vcomponents.all in order to synthesise the xpm_cdc. However, the mock cdc that I have for simulation with GHDL (vhdl only, hence no verilog libs such as xilinx xpm). In simulation, I can use the mock, but the mock entity is not declared in any packages. so my question is, can I just wrap the entity in a package? what does the syntax for this look like? I was thinking something like this:
I suppose the entity would be a component instead, but is this possible?
or can you only declare in a package?